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PM5345 Datasheet(PDF) 33 Page - PMC-Sierra, Inc |
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PM5345 Datasheet(HTML) 33 Page - PMC-Sierra, Inc |
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33 / 196 page ![]() PM5345 S/UNI-155 DATA SHEET PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19 Pin Name Type Pin No. Function RCLK Output 156 The receive clock (RCLK) output provides a timing reference for S/UNI receive outputs. RCLK is a 19.44 MHz, nominally 50% duty cycle clock. RCLK is a buffered version of PICLK when the byte serial interface is selected (RSER is tied low). RCLK is a divide by eight of RXC+/- when the bit serial interface is selected (RSER is tied high). TSER Input 26 The transmit serial input (TSER) selects the transmit line interface. TSER is tied high to select the 155.52 Mbit/s interface (on pins TXCI+, TXCI-, TXCO+, TXCO-, TXD+, and TXD-). TSER is tied low to select the 19.44 Mbyte/s interface (on pins TCLK, FPOUT, and POUT[7:0]). TXD+ TXD- Output 22 23 The transmit differential data/positive pulse outputs (TXD+, TXD-) contain either NRZ or MLT-3 encoded data when the bit serial interface is selected (TSER is tied high). When NRZ encoding is selected (FPOS/MLT is tied low), the 155.52 Mbit/s transmit STS-3c (STM-1) stream TXD+/- is updated on the falling edge of TXCO+/-. When MLT-3 encoding is selected (FPOS/MLT is tied high), the TXD+/- outputs contain the positive pulses of the MLT-3 encoded stream. TXCI+ TXCI- Input 14 13 The transmit differential clock inputs (TXCI+, TXCI-) contain the transmit clock when the bit transmit serial interface is selected. TXCI+/- is nominally a 155.52 MHz, 50% duty cycle clock. This clock provides timing for the S/UNI transmit functions. TXCI+/- may be left unconnected when S/UNI loop timing is enabled (using the S/UNI Master Control Register). |
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