PM5345 datasheet(70/196 Pages) PMC

70 / 196 page

PM5345 S/UNI-155

DATA SHEET

PMC-930305

ISSUE 4

SATURN USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

being read out of the transmit FIFO when the flushing event occurs. The flushing

event corrupts this cell, and the corrupted cell continues to be read out and is

inserted in the transmit stream. Any or all of the bytes may be corrupted in this

transmitted cell. Note that the HCS calculation occurs after the cell is corrupted,

and the result is that a corrupted cell with a valid HCS may be inserted in the

transmit stream.

FIFO overruns are indicated through a maskable interrupt and register bits. The

synchronous interface provided to an external device expects the start of a cell

(TSOC) when the first word of the selected data structure is written to the FIFO

(using TWRB). The asynchronous interface provided to an external device

indicates the cell available status (TCA). The FIFO status changes from cell

unavailable to cell available on read cell boundaries with timing derived from the

transmit line clock (POCLK). The FIFO status changes from cell available to cell

unavailable on write cell boundaries with timing aligned to the transmit write clock

(TWRB).

10.15 Line Side Interface

A 19.44 Mbyte/s TTL-compatible receive and transmit line side interface is

provided. The bit serial or byte serial line interface selection is done using the

TSER and RSER inputs.

10.15.1

Receive Interface

The low speed receive interface is a generic byte wide interface for

interconnection with an upstream serial to parallel converter, or with an upstream

byte interleaved demultiplexer.

When operating with the serial to parallel converter, the device is expected to

provide data that is demultiplexed according to SONET/SDH byte boundaries

along with a 19.44 MHz clock. In addition, the upstream serial to parallel

converter is expected to provide a framing pattern detector that performs part of

the framing function. The serial to parallel converter need not perform

descrambling as this is provided by the S/UNI. When enabled to search for

frame alignment by the S/UNI OOF output being high, the upstream device

should realign to any occurrence of the SONET/SDH framing pattern, and

provide an appropriate pulse on the S/UNI FPIN input. The upstream device

should ignore framing patterns and retain its byte alignment when the S/UNI

OOF output is low.

PM5345 Datasheet(PDF) 70 Page - PMC-Sierra, Inc