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PM5345 Datasheet(PDF) 82 Page - PMC-Sierra, Inc |
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PM5345 Datasheet(HTML) 82 Page - PMC-Sierra, Inc |
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82 / 196 page ![]() PM5345 S/UNI-155 DATA SHEET PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 68 Register 0x04: S/UNI Master Clock Monitor Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 Unused X Bit 1 R RCLKA X Bit 0 R POCLKA X This register provides activity monitoring on S/UNI clock inputs. When a monitored input makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures. Depending on the selected interface (bit serial or byte serial), this register monitors activity on the PICLK and TCLK inputs, or the RXC+/- and TXCI+/- inputs. POCLKA: The POCLK active (POCLKA) bit monitors for low to high transitions on the POCLK output. POCLKA is set high on a rising edge of POCLK, and is set low when this register is read. RCLKA: The RCLK active (RCLKA) bit monitors for low to high transitions on the RCLK output. RCLKA is set high on a rising edge of RCLK, and is set low when this register is read. |
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