LAN89218 datasheet(130/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 130

 2008-2015 Microchip Technology Inc.

6.7

TX Data FIFO Direct PIO Writes

In this mode the upper address inputs are not decoded, and any write to the LAN89218 will write the TX Data FIFO.

This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by

connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must

increment its address when accessing the LAN89218. Timing is identical to a PIO write, and the FIFO_SEL signal

has the same timing characteristics as the address lines.

Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-bit write. Note

that address lines A[2:1] are still used when the LAN89218 is operating in 32-bit and 16-bit mode. Address bits A[7:3]

are ignored.

FIGURE 6-6:

TX DATA FIFO DIRECT PIO WRITE TIMING

Note:

The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.

TABLE 6-8:

TX DATA FIFO DIRECT PIO WRITE TIMING

Symbol

Description

Min.

Typ.

Max.

Unit

tcycle

Write Cycle Time

tcsl

nCS, nWR Assertion Time

tcsh

nCS, nWR Deassertion Time

tasu

Address, END_SEL, FIFO_SEL Setup to nCS, nWR

Assertion

0ns

tah

Address, END_SEL, FIFO_SEL Hold Time

tdsu

Data Setup to nCS, nWR Deassertion

tdh

Data Hold Time

Note:

A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when

either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.

tah

tdsu

A[2:1], END_SEL

nCS, nWR

Data Bus

FIFO_SEL

tdh

tcsh

tcycle

tcsl

tasu

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