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LAN89218 Datasheet(PDF) 132 Page - Microchip Technology |
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LAN89218 Datasheet(HTML) 132 Page - Microchip Technology |
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132 / 148 page ![]() LAN89218 DS60001255B-page 132 2008-2015 Microchip Technology Inc. 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN89218: FIGURE 6-8: EEPROM TIMING TABLE 6-10: EEPROM TIMING VALUES Symbol Description Min. Typ. Max. Unit tckcyc EECLK Cycle time 1110 1130 ns tckh EECLK High time 550 570 ns tckl EECLK Low time 550 570 ns tcshckh EECS high before rising edge of EECLK 1070 ns tcklcsl EECLK falling edge to EECS low 30 ns tdvckh EEDIO valid before rising edge of EECLK (OUTPUT) 550 ns tckhdis EEDIO disable after rising edge EECLK (OUT- PUT) 550 ns tdsckh EEDIO setup to rising edge of EECLK (INPUT) 90 ns tdhckh EEDIO hold after rising edge of EECLK (INPUT) 0ns tckldis EECLK low to data disable (OUTPUT) 580 ns tcshdv EEDIO valid after EECS high (VERIFY) 600 ns tdhcsl EEDIO hold after EECS low (VERIFY) 0 ns tcsl EECS low 1070 ns EECLK EEDIO (OUTPUT) EEDIO (INPUT) EECS tckldis tcshckh EEDI (VERIFY) tckh tckl tckcyc tcklcsl tcsl tdvckh tckhdis tdsckh tdhckh tdhcsl tcshdv |
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