AL875 datasheet(12/34 Pages) ETC

12 / 34 page

AL875

Preliminary version subject to change without notice

January 25, 2001

logic clock)

CKBO

OUT (CMOS)

Output clock B, with phase adjustment

CKADCO

OUT (CMOS)

ACD sampling clock output (in phase with ADC

sampling clock)

HSFB

OUT (CMOS)

Clock divided by N for external PLL circuits

Reset, I

2C and Configuration Pins

/RESET

IN (CMOSu)

Reset pin (active LOW)

PWRDN

IN (CMOSd)

Power-Down control (Active HIGH)

SCL

IN (CMOSs)

I2C serial clock input

SDA

INOUT

(CMOSsu)

I2C serial data input/output

ADDR[2:1]

IN (CMOSd)

34, 33

I2C address control input

CKINTEN

IN (CMOSd)

Test pin, pulled down for normal operation.

Reserved for AL876 internal clock enable (LO:

external clock, HI: internal PLL clock)

/OE

IN (CMOS)

Output enable (when OE is HIGH, the outputs

are in HI-Z)

INV

IN (CMOSd)

The invert control of the ADC sampling clock

Test Pins

ADTEST3

IN (CMOSu)

Internal ADC test pins 3

ADTEST[2:1]

IN (CMOSd)

36, 35

Internal ADC test pins 2~1

TESTIN4

IN (CMOSd)

Test signal input 4

TESTIN[3:0]

IN (CMOS)

1, 2, 3, 4

Test signal input 3~0

Power, Ground and No Connect

VDD

POWER

5, 40, 95

Digital power supply

VDDR

POWER

Red channel ADC output power supply

VDDG

POWER

Green channel ADC output power supply

VDDB

POWER

Blue channel ADC output power supply

VDDPLL

POWER

Digital power supply; reserved for AL876 PLL

power supply

VDDAR

POWER

Red channel analog power supply

VDDAG

POWER

Green channel analog power supply

VDDAB

POWER

Blue channel analog power supply

VDDAPLL

POWER

Analog power supply. Reserved for PLL analog

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