AL875

Preliminary version subject to change without notice

January 25, 2001

18

Details about these registers can be found in the Register Definition section.

6.5 Clock Phase Test (for Jitter-reduction)

The AL875 provides a proprietary clock phase test mode for jitter-reduction.

Jitters may be

experienced when sampling clock frequency and/or phase is not accurate. The AL875 can sample

twice (with slightly different clock phases) on each odd or even pixel and count the total output value

difference of the two phases (delay controlled by register #07h). This information (stored in registers

#08h and #09h) is then available for the micro-controller to adjust the sampling clock frequency and

phase for optimization. Additional reference can be found in the Register Definition section.

INPUT

ACTIVE

REGION

HSYNC

WVDE_ST,

#25h<2:0> & #26h<7:0>

WHDE_END,

#23h<2:0> & #24h<7:0>

WVDE_END,

#27h<2:0> & #28h<7:0>

WHDE_ST,

#21h<2:0>

& #22h<7:0>

Threshold = DATA_TH, #11h

When horizontal and vertical thresholds are different:

Threshold horizontal = DATA_TH, #11h

Threshold vertical = VDATA_TH, #0Fh, Enabled by #06h<7>

AL875-10 Whole-frame position detection