AL875

Preliminary version subject to change without notice

January 25, 2001

20

The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA

line (HIGH) during the acknowledge clock pulse, but the AL875 does not pull it down during this

stage.

<DATA>:

Data byte write to or read from the register index.

In read operation, the host must release the SDA line (high) before the first clock pulse is

transmitted to the AL875.

<P>:

Stop signal

SCL SDA

High Low

High High

The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH.

Suppose data F0h is to be written to register 0Fh using write slave address 98h, the timing is as

follows:

Suppose data is to be read from register 55h using read slave address 99h, the timing is as follows:

Start

Slave addr = 98h Ack

Ack

Ack Stop

Index = 0Fh

Data = F0h

SDA

SCL

AL875-04 I2C Write timing

Start

Slave addr = 98h

Ack

Ack

Ack

Index = 55h

Read slave addr = 99h

SDA

SCL

AL875-05 I2C Read timing

NAck

Stop

Data read cycle

Stop

Start