AL875

Preliminary version subject to change without notice

January 25, 2001

15

6.2 ADC outputs

The ADC outputs are straight binary. An output enable pin (/OE, active LOW) toggles the output

status between active and high-impedance (/OE = HIGH). The timing should be checked carefully if

the output capacitive load is more than 10 pF.

6.3 Clock Distribution

The ADCs’ sampling clock is usually from an external PLL clock source. The AL875 provides a PLL

reference clock CKREFO (with phase adjustment) for the external PLL to generate the pixel clock to

CKEXT pin as the ADC sampling clock. If the PLL requires a feedback signal, it is provided by the

AL875 HSFB pin which signal is obtained from CKEXT divided by N. The PLL programming can be

either by the external PLL chip (if available) or by the AL875 registers.

In order to adjust the phase of the reference clock for optimal PLL quality, the CKREFO has

programmable delay from the CKREF input, which is usually a HSYNC signal. Each programmable

increment is equivalent to approximately 1.6ns. The CKREF delay adjustment diagram is as follows:

The PLL-generated pixel clock is input from the CKEXT pin, then distributed to different internal or

output pins with different delay for different purposes. The internal logic clock is available at CKAO

pin.

The delay-adjustable clock is available at CKBO, which programmability is useful for the

setup/hold time optimization for the LCD controller or any chip that captures the output of the

AL875. The ADC sampling clock is also available at CKADCO pin. The HSFB divider can be up to

4096. The clock distribution circuitry is illustrated in the following diagram:

INV

DELAY

CKREF

4

PHASE A

#0Ch<7:4>

CKREFO-INV

#02h<4>

CKREFO

AL875-07a Clock Reference Delay

Input/Output pin

1 delay = 1.6ns

Max. 15 delays = 24ns