AD7761BSTZ datasheet(32/76 Pages) AD

32 / 76 page

Data Sheet

AD7761

Rev. A | Page 31 of 75

Table 12. Requirements to Operate the AD7761

Requirement

Description

Power Supplies

5 V AVDD1 supply, 2.25 V to 5 V AVDD2 supply, 1.8 V or 2.5 V to 3.3 V IOVDD supply (ADP7104/ADP7118)

External Reference

2.5 V, 4.096 V, or 5 V (ADR4525, ADR4540, or ADR4550)

External Driver Amplifiers

The ADA4896-2, the ADA4940-1/ADA4940-2, the ADA4805-2, and the ADA4807-2

External Clock

Crystal or a CMOS/LVDS clock for the ADC modulator sampling

FPGA or DSP

Input/output voltage of 2.5 V to 3.6 V, or 1.8 V (see the 1.8 V IOVDD Operation section)

Table 13. Speed, Dynamic Range, THD, and Power Overview; Eight Channels Active, Decimate by 321

Power

Mode

Output

Data Rate

(kSPS)

THD

(dB)

Sinc5 Filter

Wideband Filter

Dynamic

Range (dB)

Bandwidth

(kHz)

Power Dissipation

(mW per channel)

Dynamic

Range (dB)

Bandwidth

(kHz)

Power Dissipation

(mW per channel)

Fast

256

−115

97.7

52.224

97.7

110.8

Median

128

−120

97.7

26.112

97.7

55.4

Low Power

−120

97.7

6.528

8.5

97.7

13.9

9.5

Analog precharge buffers on, precharge reference buffers and VCM disabled, typical values, AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, VREF = 4.096 V, MCLK = 32.768 MHz,

DCLK = MCLK/4, TA = 25°C.

POWER SUPPLIES

The AD7761 has three independent power supplies: AVDD1

(given by the AVDD1A pin and the AVDD2A pin), AVDD2

(given by the AVDD2A pin and the AVDD2B pin), and IOVDD.

The reference potentials for these supplies are AVSS and DGND.

Tie all the AVSS supply pins (AVSS1A, AVSS1B, AVSS2A, AVSS2B,

and AVSS) to the same potential with respect to DGND. AVDD1A,

AVDD1B, AVDD2A, and AVDD2B are referenced to this AVSS

rail. IOVDD is referenced to DGND.

The supplies can be powered within the following ranges:

•

AVDD1 = 5 V ± 10%, relative to AVSS

•

AVDD2 = 2 V to 5.5 V, relative to AVSS

•

IOVDD (with internal regulator) = 2.25 V to 3.6 V, relative

to DGND

•

IOVDD (bypassing regulator) = 1.72 V to 1.88 V, relative to

DGND

•

AVSS = −2.75 V to 0 V, relative to DGND

The AVDD1A and AVDD1B (AVDD1) supplies power the analog

front end, reference input, and common-mode output circuitry.

AVDD1 is referenced to AVSS, and all AVDD1 supplies must be

tied to the same potential with respect to AVSS. If AVDD1 supplies

are used in a ±2.5 V split supply configuration, the ADC inputs are

truly bipolar. When using split supplies, reference the absolute

maximum ratings, which apply to the voltage allowed between

the AVSS and IOVDD supplies.

The AVDD2A and AVDD2B (AVDD2) supplies connect to

internal 1.8 V analog LDO regulators. The regulators power the

ADC core. AVDD2 is referenced to AVSS, and all AVDD2 supplies

must be tied to the same potential with respect to AVSS. The

voltage on AVDD2 can range from 2 V (minimum) to 5.5 V

(maximum), with respect to AVSS.

IOVDD powers the internal 1.8 V digital LDO regulator. This

regulator powers the digital logic of the ADC. IOVDD also sets

the voltage levels for the SPI interface of the ADC. IOVDD is

referenced to DGND, and the voltage on IOVDD can vary from

2.25 V (minimum) to 3.6 V (maximum), with respect to DGND.

IOVDD can also be configured to run at 1.8 V. In this case, IOVDD

and DREGCAP must be tied together and must be within the

range of 1.72 V (minimum) to 1.88 V (maximum), with respect

to DGND. See the 1.8 V IOVDD Operation section for more

information on operating the AD7761 at 1.8 V IOVDD.

Recommended Power Supply Configuration

Analog Devices, Inc., has a wide range of power management

products to meet the requirements of most high performance

signal chains.

An example of a power solution that uses the ADP7118 is shown

in Figure 49. The ADP7118 provides positive supply rails for

optimal converter performance, creating either a single 5 V,

3.3 V, or dual AVDD1 and AVDD2/IOVDD, depending on the

required supply configuration. The ADP7118 can operate from

input voltages of up to 20 V.

ADP7118

LDO

12V

INPUT

5V: AVDD1x

3.3V: AVDD2x/IOVDD

ADP7118

LDO

Figure 49. Power Supply Configuration

Alternatively, the ADP7112 or ADP7104 can be selected for

powering the AD7761. Refer to the AN-1120 Application Note

for more information regarding low noise LDO performance

and power supply filtering.

AD7761BSTZ Datasheet(PDF) 32 Page - Analog Devices

AD7761BSTZ Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL