AD7761BSTZ datasheet(49/76 Pages) AD

49 / 76 page

AD7761

Data Sheet

Rev. A | Page 48 of 75

CALIBRATION

In SPI control mode, the AD7761 offers users the ability to adjust

offset, gain, and phase delay on a per channel basis.

Offset Adjustment

The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_

OFFSET_LSB registers are 24-bit, signed twos complement

registers for channel offset adjustment. If the channel gain setting is

at its ideal nominal value of 0x555555, an LSB of offset register

adjustment changes the digital output by −1/192 LSBs. For

example, changing the offset register from 0 to 4800 changes the

digital output by −25 LSBs. Because offset calibration occurs

before gain calibration, the ratio of −1/192 changes linearly with

gain adjustment via the Channel x gain registers (see Table 53).

After a reset or power cycle, the offset register values revert to the

default factory setting.

Gain Adjustment

Each ADC channel has an associated gain coefficient. The

coefficient is stored in three single-byte registers split up as

MSB, MID, and LSB. Each of the gain registers are factory

programmed. Nominally, this gain is around the value 0x555555

(for an ADC channel). The user can overwrite the gain register

setting. However, after a reset or power cycle, the gain register

values revert to the hard coded programmed factory setting.

Calculate the approximate result that is output using the

following formula:

300

194

1024

)

(













−

Gain

Offset

Data

REF

where:

Offset is the offset register setting.

Gain is the gain register setting.

Sync Phase Offset Adjustment

The AD7761 has one synchronization signal for all channels.

The sync phase offset register allows the user to vary the phase

delay on each channel relative to the synchronization edge

received on the SYNC_IN pin.

By default, all ADC channels react simultaneously to

the SYNC_IN pulse. The sync phase registers can be

programmed to equalize known external phase differences on

the ADC input channels, relative to one another. The range of

phase compensation is limited to a maximum of one conversion

cycle, and the resolution of the correction depends on the

decimation rate in use.

Table 29 displays the resolution and register bits used for phase

offset for each decimation ratio.

Table 29. Phase Delay Resolution

Decimation

Ratio

Resolution

Steps

Sync Phase Offset

×32

1/fMOD

[7:3]

×64

1/fMOD

[7:2]

×128

1/fMOD

128

[7:1]

×256

1/fMOD

256

[7:0]

×512

2/fMOD

256

[7:0]

×1024

4/fMOD

256

[7:0]

Adjusting the sync phase of channels can affect the time to the

first DRDY pulse after the sync pulse, as well as the time to Bit 6

of the header status (filter not settled data bit) being cleared,

that is, the time to settled data.

If all channels are using the sinc5 filter, the time to the

first DRDY pulse is not affected by the adjustment of the sync

phase offset, assuming that at least one channel has zero sync

phase offset adjustment. If all channels have a nonzero sync phase

offset setting, the time to the first DRDY pulse is delayed

according to the channel that has the least offset applied.

Channels with a sync offset adjustment setting that delays the

internal sync signal, relative to other channels, may not output

settled data until after the next DRDY pulse. In other words,

there may be a delay of one ODR period between the settled

data being output by the AD7761 for the channels with added

phase delay.

If all channels are using the wideband filter, the time to the

first DRDY pulse and the time to settled data is delayed

according to the channel with the maximum phase delay

setting. In this case, the interface waits for the latest channel and

outputs data for all channels when that channel is ready.

AD7761BSTZ Datasheet(PDF) 49 Page - Analog Devices

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