AD7761BSTZ datasheet(33/76 Pages) AD

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AD7761

Data Sheet

Rev. A | Page 32 of 75

1.8 V IOVDD Operation

The AD7761 contains an internal 1.8 V LDO on the IOVDD

supply to regulate the IOVDD down to the operating voltage of the

digital core. This internal LDO allows the internal logic to operate

efficiently at 1.8 V and the input/output logic to operate at the

level set by IOVDD. The IOVDD supply is rated from 2.25 V to

3.6 V for normal operation, and 1.8 V for LDO bypass setup.

START

SYNC_IN

IOVDD

DREGCAP

DGND

SYNC_OUT

28 29 30 31 32

1.8V IOVDD

SUPPLY

Figure 50. DREGCAP and IOVDD Connection Diagram for 1.8 V IOVDD

Operation

Users can bypass the LDO by shorting the DREGCAP pin to

IOVDD (see Figure 50), which pulls the internal LDO out of

regulation and sets the internal core voltage and input/output

logic levels to the IOVDD level. When bypassing the internal

LDO, the maximum operating voltage of the IOVDD supply is

equal to the maximum operating voltage of the internal digital core,

which is 1.72 V to 1.88 V.

Analog Supply Internal Connectivity

The AD7761 has two analog supply rails, AVDD1 and AVDD2,

which are both referred to AVSS. These supplies are completely

separate from the digital pins, IOVDD, DREGCAP, and DGND. To

achieve optimal performance and isolation of the ADCs, more than

one device pin supplies these analog rails to the internal ADCs.

•

AVSS1A (Pin 3) and AVSS2A (Pin 62) are internally

connected.

•

AVSS (Pin 54) is connected to the substrate, and is connected

internally to AVSS1B (Pin 46) and AVSS2B (Pin 51).

•

The following supply and reference input pins are separate

on chip: AVDD1A, AVDD1B, AVDD2A, AVDD2B,

REF1+, REF1−, REF2+, and REF2−.

The details of which individual supplies are shorted internally are

given in this section for informational purposes. In general,

connect the supplies as described in the Power Supplies section.

DEVICE CONFIGURATION

The AD7761 has independent paths for reading data from the

ADC conversions and for controlling the device functionality.

For control, the device can be configured in either of two

modes. The two modes of configuration are as follows:

•

Pin control mode: pin strapped digital logic inputs (which

allows a subset of the configurability options)

•

SPI control mode: over a 3-wire or 4-wire SPI interface

(complete configurability)

On power-up, the state of the PIN/SPI pin determines the mode

used. Immediately after power-up, the user must apply a soft or

hard reset to the device when using either control mode.

Interface Data Format

When operating the device, the data format of the serial interface is

determined by the FORMATx pins. Table 30 shows that each ADC

can be assigned a DOUTx pin, or, alternatively, the data can be

arranged to share the DOUTx pins in a time division multiplexed

manner. For more details, see the Data Interface section.

PIN CONTROL MODE

Pin control mode eliminates the need for an SPI communication

interface. When a single known configuration is required by the

user, or when only limited reconfiguration is required, the number

of signals that require routing to the digital host can be reduced

using this mode. Pin control mode is useful in digitally isolated

applications where minimal adjustment of the configuration is

needed. Pin control offers a subset of the core functionality and

ensures a known state of operation after power-up, reset, or a

fault condition on the power supply. In pin control mode, the

analog input precharge buffers are enabled by default for best

performance. The reference input precharge buffers are disabled

in pin control mode.

After any change to the configuration in pin control mode, the

user must provide a sync signal to the AD7761 by applying the

appropriate pulse to the START pin or the SYNC_IN pin to

ensure that the configuration changes are applied correctly to

the ADC and the digital filters.

Setting the Filter

The filter function chooses between the two filter settings. In

pin control mode, all ADC channels use the same filter type,

which is selected by the FILTER pin, as shown in Table 14.

Table 14. FILTER Control Pin

Logic Level

Function

Sinc5 filter selected

Wideband filter selected

AD7761BSTZ Datasheet(PDF) 33 Page - Analog Devices

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