AD7761BSTZ datasheet(29/76 Pages) AD

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AD7761

Data Sheet

Rev. A | Page 28 of 75

For example, to maximize the speed of conversion or input

bandwidth in fast mode, an MCLK of 32.768 MHz is required

and MCLK_DIV = 4 must be selected for a modulator

frequency of 8.192 MHz.

Table 9. Recommended fMOD Range for Each Power Mode

Power Mode

Recommended fMOD (MHz), MCLK = 32.768 MHz

Low Power

0.036 to 1.024

Median

1.024 to 4.096

Fast

4.096 to 8.192

Control of the settings for the power mode, the modulator

frequency, and the data clock frequency differs in pin control

mode vs. SPI control mode.

In SPI control mode, the user can program the power mode, the

MCLK divider (MCLK_DIV), and the DCLK frequency using

and MCLK_DIV allows full freedom in the MCLK speed selection

to achieve a target modulator frequency.

In pin control mode, the MODEx pins determine the power

mode, the modulator frequency, and the DCLK frequency. The

modulator frequency tracks the power mode. This means that

fMOD is fixed at MCLK/32 for low power mode, MCLK/8 for

median mode, and MCLK/4 for fast mode (see Table 18).

Example of Power vs. Noise Performance Optimization

Depending on the bandwidth of interest for the measurement,

the user can choose a strategy of either lowest current consumption

or highest resolution. This choice is due to an overlap in the

coverage of each power mode. The AD7761 offers the ability to

balance the MCLK division ratio with the rate of decimation

(averaging) set in the digital filter. Lower power can be achieved

by using lower modulator clock frequencies. Conversely, the

highest resolution can be achieved by using higher modulator

clock frequencies and maximizing the amount of oversampling.

As an example, consider a system constraint with a maximum

available MCLK of 16 MHz. The system is targeting a measure-

ment bandwidth of approximately 25 kHz with the wideband

filter, setting the output data rate of the AD7761 to 62.5 kHz.

Because of the low MCLK frequency available and the system

power budget, median power mode is used.

In median power mode, this 25 kHz input bandwidth can be

achieved by setting the MCLK division and decimation ratio to

balance, using two configurations (Configuration A and

Configuration B). This flexibility is possible in SPI control

mode only.

Configuration A

To maximize the dynamic range, use the following settings:

•

MCLK = 16 MHz

•

Median power

•

fMOD = MCLK/4

•

Decimation = ×64 (digital filter setting)

•

ODR = 62.5 kHz

This configuration maximizes the available decimation rate (or

oversampling ratio) for the bandwidth required and MCLK rate

available. The decimation averages the noise from the modulator,

maximizing the dynamic range.

Configuration B

To minimize power, use the following settings:

•

MCLK = 16 MHz

•

Median power

•

fMOD = MCLK/8

•

Decimation = ×32 (digital filter setting)

•

ODR = 62.5 kHz

This configuration reduces the clocking speed of the modulator

and the digital filter.

When compared to Configuration A, Configuration B saves

48 mW of power. The trade-off in the case of Configuration B is

that the digital filter must run at a 2× lower decimation rate.

This 2× reduction in decimation rate (or oversampling ratio)

results in a 3 dB reduction in the dynamic range vs. Config-

uration A.

Clocking Out the ADC Conversion Results (DCLK)

The AD7761 DCLK is a divided version of the master clock

input. As shown in Figure 47, the DCLK_DIV setting determines

the speed of the DCLK. DCLK is a continuous clock.

The user can set the DCLK frequency rate to one of four divisions

of MCLK: MCLK/1, MCLK/2, MCLK/4, and MCLK/8. Because

there are eight channels and 24 bits of data per conversion, the

conversion time and the setting of DCLK directly determine the

number of data output lines that are required via the FORMATx

pin settings. Thus, the intended minimum decimation and desired

DCLK_DIV setting must be understood prior to choosing the

setting of the FORMATx pins.

NOISE PERFORMANCE AND RESOLUTION

Table 10 and Table 11 show the noise performance for the

wideband and sinc5 digital filters of the AD7761 for various

output data rates and power modes. The noise values specified

are typical for the bipolar input range with an external 4.096 V

reference (VREF).

The LSB size with 4.096 V reference is 125 µV, and is calculated

as follows:

LSB (V) = (2 × VREF)/216

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