AD7761BSTZ datasheet(64/76 Pages) AD

64 / 76 page

Data Sheet

AD7761

Rev. A | Page 63 of 75

CHANNEL MODE A REGISTER

Address: 0x01, Reset: 0x0D, Name: Channel Mode A

Two mode options are available on the AD7761 ADCs. The channel modes are defined by the contents of the Channel Mode A and

Channel Mode B registers. Each mode is then mapped as desired to the required ADC channel. Channel Mode A and Channel Mode B

allow different filter types and decimation rates to be selected and mapped to any of the ADC channels.

When different decimation rates are selected, the AD7761 outputs a data ready signal at the fastest selected decimation rate. Any channel

that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero

and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output:

Header and Data section).

Table 35. Bit Descriptions for Channel Mode A

Bits

Bit Name

Settings

Description

Reset

Access

FILTER_TYPE_A

Filter selection

0x1

Wideband filter

Sinc5 filter

[2:0]

DEC_RATE_A

Decimation rate selection

0x5

000

×32

001

×64

010

×128

011

×256

100

×512

101

×1024

110

×1024

111

×1024

CHANNEL MODE B REGISTER

Address: 0x02, Reset: 0x0D, Name: Channel Mode B

Table 36. Bit Descriptions for Channel Mode B

Bits

Bit Name

Settings

Description

Reset

Access

FILTER_TYPE_B

Filter selection

0x1

Wideband filter

Sinc5 filter

[2:0]

DEC_RATE_B

Decimation rate selection

0x5

000

×32

001

×64

010

×128

011

×256

100

×512

101

×1024

110

×1024

111

×1024

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