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AD7761BSTZ Datasheet(PDF) 18 Page - Analog Devices

Part # AD7761BSTZ
Description  8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW
PDF  76 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7761BSTZ Datasheet(HTML) 18 Page - Analog Devices

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Data Sheet
AD7761
Rev. A | Page 17 of 75
Pin No.
Mnemonic
Type1
Description
12, 13,
14, 15
MODE0/GPIO0,
MODE1/GPIO1,
MODE2/GPIO2,
MODE3/GPIO3
DI/DI/O
Mode Selection/General-Purpose Input/Output Pin 0 to Pin 3.
In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling
power consumption, DCLK frequency, and the ADC conversion type, allowing one-shot
conversion operation.
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-
purpose input/output pins (GPIO4 to GPIO0).
16
ST0/CS
DI
Standby 0/Chip Select Input.
In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface.
17
ST1/SCLK
DI
Standby 1/Serial Clock Input.
In pin control mode, a Logic 1 places Channel 4 to Channel 7 into standby mode.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into
standby mode, the crystal circuitry is also disabled for maximum power saving. Channel 4 must
be enabled while the external crystal is used on the AD7761.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface.
18
DEC1/SDI
DI
Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7761
register bank.
19
DEC0/SDO
DI/O
Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.
In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7761
registers.
20
DOUT7
DI/O
Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDY. This pin acts as
a digital input from a separate AD7761 device if configured in a synchronized multidevice daisy
chain when the FORMATx pins are configured as 01.To use the AD7761 in a daisy chain, hardwire the
FORMATx pins as either 01, 10, or 11, depending on the best interfacing format for the application.
When FORMATx is set to 10 or 11, connect this pin to ground through a pull-down resistor.
21
DOUT6
DI/O
Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDY. This pin acts as
a digital input from a separate AD7761 device if configured in a synchronized multidevice daisy
chain. To use this pin in a daisy chain, hardwire the FORMATx pins as either 01, 10, or 11,
depending on the best interfacing format for the application.
22
DOUT5
DO
Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.
23
DOUT4
DO
Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.
24
DOUT3
DO
Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
25
DOUT2
DO
Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
26
DOUT1
DO
Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
27
DOUT0
DO
Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY
28
DCLK
DO
ADC Conversion Data Clock. This pin clocks conversion data out to the digital host, either digital
signal processing (DSP) or field programmable gate array (FPGA). This pin is synchronous
with DRDY and any conversion data output on DOUT0 to DOUT7 and is derived from the MCLK
signal. This pin is unrelated to the control SPI interface.
29
DRDY
DO
Data Ready. Periodic signal output framing the conversion results from the eight ADCs. This pin
is synchronous to DCLK and DOUT0 to DOUT7.
30
RESET
DI
Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to
perform a hard or soft reset.
31
XTAL1
DI
Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND.
In SPI control mode, when using a crystal source, the FILTER pin must be set to Logic 1 for
correct operation.



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