AD7761BSTZ datasheet(28/76 Pages) AD

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Data Sheet

AD7761

Rev. A | Page 27 of 75

THEORY OF OPERATION

The AD7761 is an 8-channel, simultaneously sampled, low

noise, Σ-∆ ADC.

Each ADC within the AD7761 employs a Σ-Δ modulator whose

clock runs at a frequency of fMOD. The modulator samples the

inputs at a rate of 2 × fMOD, to convert the analog input into an

equivalent 16-bit digital representation, and these samples there-

fore represent a quantized version of the analog input signal.

The Σ-Δ conversion technique is an oversampled architecture.

This oversampled approach spreads the quantization noise over

a wide frequency band (see Figure 44). To reduce the quantization

noise in the signal band, the high order modulator shapes the noise

spectrum so that most of the noise energy is shifted out of the

band of interest (see Figure 45). The digital filter that follows the

modulator removes the large out of band quantization noise

(see Figure 46).

For further information on the basics as well as more advanced

concepts of Σ-Δ ADCs, see the MT-022 Tutorial and the

MT-023 Tutorial.

Digital filtering has certain advantages over analog filtering. First, it

is insensitive to component tolerances and the variation of

component parameters over time and temperature. And because

digital filtering on the AD7761 occurs after the analog-to-digital

conversion, it can remove some of the noise injected during the

conversion process; analog filtering cannot remove noise

injected during conversion. Second, the digital filter combines

low pass-band ripple with a steep roll-off and high stop-band

attenuation, while also maintaining a linear phase response,

which is difficult to achieve in an analog filter implementation.

QUANTIZATION NOISE

fMOD/2

BAND OF INTEREST

Figure 44. Σ-Δ ADC Quantization Noise (Linear Scale X-Axis)

NOISE SHAPING

BAND OF INTEREST

fMOD/2

Figure 45. Σ-Δ ADC Noise Shaping (Linear Scale X-Axis)

DIGITAL FILTER CUTOFF FREQUENCY

BAND OF INTEREST

fMOD/2

Figure 46. Σ-Δ ADC Digital Filter Cutoff Frequency (Linear Scale X-Axis)

CLOCKING, SAMPLING TREE, AND POWER SCALING

The AD7761 includes multiple ADC cores. Each of these ADCs

receives the same master clock signal, MCLK. The MCLK signal

can be sourced from one of three options: a CMOS clock, a crystal

connected between the XTAL1 and XTAL2 pins, or in the form

of an LVDS signal. The MCLK signal received by the AD7761 is

used to define the modulator clock rate, fMOD, and in turn the

sampling frequency of the modulator of 2 × fMOD. The same

MCLK signal is also used to define the digital output clock,

DCLK. The fMOD and DCLK internal signals are synchronous

with MCLK.

Figure 47 shows the clock tree from the MCLK input to the

modulator, the digital filter, and the DCLK output. There are

divider settings for MCLK and DCLK. These dividers, in

conjunction with the power mode and digital filter decimation

settings, are key to the operation of the AD7761.

The AD7761 has the ability to scale power consumption vs. the

input bandwidth or desired noise. The user controls two para-

meters to achieve this: MCLK division and power mode. When

combined, these two settings determine the clock frequency of the

modulator (fMOD) and the bias current supplied to each modulator.

The power mode (fast, median, or low power) sets the noise, speed

capability, and current consumption of the modulator. The

power mode is the dominant control for scaling the power

consumption of the ADC. All settings of MCLK division and

power mode apply to all ADC channels.

DCLK_DIV

00: DCLK = MCLK/8

01: DCLK = MCLK/4

10: DCLK = MCLK/2

11: DCLK = MCLK/1

MCLK_DIV

MCLK/4

MCLK/8

MCLK/32

POWER MODES:

FAST

MEDIAN

LOW POWER

DECIMATION RATES = ×32, ×64,

×128, ×256, ×512, ×1024

DIGITAL

FILTER

DCLK

DRDY

DOUTx

DATA

INTERFACE

CONTROL

ADC

MODULATOR

Figure 47. Sampling Structure, Defined by the MCLK, DCLK_DIV, and

MCLK_DIV Settings

The modulator clock frequency (fMOD) is determined by selecting

one of three clock divider settings: MCLK/4, MCLK/8, or

MCLK/32.

Although the MCLK division and power modes are independent

settings, there are restrictions that must be adhered to. A valid

range of modulator frequencies exists for each power mode.

Table 9 describes this recommended range, which allows the

device to achieve the best performance while minimizing power

consumption. The AD7761 specifications do not cover the

performance and function beyond the maximum fMOD for a given

power mode.

AD7761BSTZ Datasheet(PDF) 28 Page - Analog Devices

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