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LAN9220 Datasheet(PDF) 110 Page - Microchip Technology |
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LAN9220 Datasheet(HTML) 110 Page - Microchip Technology |
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110 / 142 page ![]() LAN9220 DS00002417A-page 110 2006-2017 Microchip Technology Inc. 5.5.9 SPECIAL MODES Note 5-4 When MODE=111, the register 0 bits 13 and 8 are variable dependent on the auto-negotiated speed and duplex. Index (In Decimal): 18 Size: 16-bits Address Description Type Default 15-8 Reserved RW, NASR 7:5 MODE: PHY Mode of operation. Refer to Table 5-9 for more details. RW, NASR 111 4:0 PHYAD: PHY Address: The PHY Address is used for the SMI address. RW, NASR 00001b TABLE 5-9: MODE CONTROL MODE Mode Definitions Default Register Bit Values Register 0 Register 4 [13,12,10,8] [8,7,6,5] 000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A 001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A 010 100Base-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive. 1000 N/A 011 100Base-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive. 1001 N/A 100 100ase-TX Half Duplex is advertised. Auto- negotiation enabled. CRS is active during Transmit & Receive. 1100 0100 101 Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 1100 0100 110 Reserved - Do not set the LAN9220 in this mode. N/A N/A 111 All capable. Auto-negotiation enabled. X10X Note 5-4 1111 |
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