LAN9220 datasheet(114/142 Pages) MICROCHIP

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LAN9220

DS00002417A-page 114

 2006-2017 Microchip Technology Inc.

6.0

TIMING DIAGRAMS

6.1

Equivalent Test Load

Output timing specifications assume an equivalent test load as illustrated in Figure 6-1 below.

6.2

Host Interface Timing

The LAN9220 supports the following host cycles:

Read Cycles:

• PIO Reads (nCS or nRD controlled)

• PIO Burst Reads (nCS or nRD controlled)

• RX Data FIFO Direct PIO Reads (nCS or nRD controlled)

• RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)

Write Cycles:

• PIO writes (nCS and nWR controlled)

• TX Data FIFO direct PIO writes (nCS or nWR controlled)

All timing measurements were verified under the following conditions:

Temperature: ................................................................................................................................................0oC to +70oC

Load Capacitance (VDDVARIO = 3.3V +/- 300mV): ................................................................................................. 25pF

Load Capacitance (VDDVARIO = 2.5V +/- 10%): ..................................................................................................... 10pF

Load Capacitance (VDDVARIO = 1.8V +/- 10%): ..................................................................................................... 10pF

6.2.1

SPECIAL RESTRICTIONS ON BACK-TO-BACK WRITE/READ CYCLES

It is important to note that there are specific restrictions on the timing of back-to-back write-read operations. These

restrictions concern reading the control registers after any write cycle to the LAN9220 device. In many cases there is a

required minimum delay between writing to the LAN9220, and the subsequent side effect (change in the control register

value). For example, when writing to the TX Data FIFO, it takes up to 165ns for the level indication to change in the

TX_FIFO_INF register.

In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced.

These periods are specified in Table 6-1, "Read After Write Timing Rules". The host processor is required to wait the

specified period of time after any write to the LAN9220 before reading the resource specified in the table. These wait

periods are for read operations that immediately follow any write cycle. Note that the required wait period is dependent

upon the register being read after the write.

Performing "dummy" reads of the BYTE_TEST register is a convenient way to ensure that the minimum write-to-read

timing restriction is met. Table 6-1 also shows the number of dummy reads that are required before reading the register

indicated. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (165ns). For micro-

FIGURE 6-1:

EQUIVALENT TEST LOAD

Note:

The specified test load used for output timing is dependent on VDDVARIO.

OUTPUT

Test load varies dependent on VDDVARIO:

VDDVARIO = 3.3V ± 300mV: 25pF

VDDVARIO = 2.5V ± 10%: 10pF

VDDVARIO=1.8V ± 10%: 10pF

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