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LAN9220 Datasheet(PDF) 115 Page - Microchip Technology |
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LAN9220 Datasheet(HTML) 115 Page - Microchip Technology |
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115 / 142 page  2006-2017 Microchip Technology Inc. DS00002417A-page 115 LAN9220 processors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as long as the min- imum time period is met. TABLE 6-1: READ AFTER WRITE TIMING RULES Register Name Minimum Wait Time for Read Following Any Write Cycle (in ns) Number of BYTE_TEST Reads (Assuming Tcycle of 165ns) ID_REV 0 0 IRQ_CFG 165 1 INT_STS 165 1 INT_EN 165 1 BYTE_TEST 0 0 FIFO_INT 165 1 RX_CFG 165 1 TX_CFG 165 1 HW_CFG 165 1 RX_DP_CTRL 165 1 RX_FIFO_INF 0 0 TX_FIFO_INF 165 1 PMT_CTRL 330 2 GPIO_CFG 165 1 GPT_CFG 165 1 GPT_CNT 165 1 WORD_SWAP 165 1 FREE_RUN 330 2 RX_DROP 0 0 MAC_CSR_CMD 165 1 MAC_CSR_DATA 165 1 AFC_CFG 165 1 E2P_CMD 165 1 E2P_DATA 165 1 |
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