LAN9220 datasheet(117/142 Pages) MICROCHIP

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DS00002417A-page 117

LAN9220

6.3

PIO Reads

PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are

latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per-

formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between

cycles for the period specified.

Note 6-2

When VDDVARIO is 3.3V or 2.5V, the maximum Tdoff time is 7ns. When VDDVARIO is 1.8V, the

maximum Tdoff time is 9ns.

Note:

Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.

FIGURE 6-2:

PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-3:

PIO READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Read Cycle Time

165

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time (see Note below)

133

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address Setup to nCS, nRD Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

Note 6-2

tdoh

Data Output Hold Time

Note:

A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS

and nRD are deasserted. They may be asserted and deasserted in any order. Parameters tcsh and tcsl must

be extended using wait states to meet the tcycle minimum.

Data Bus

nCS, nRD

A[7:1]

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