LAN9220 datasheet(120/142 Pages) MICROCHIP

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LAN9220

DS00002417A-page 120

 2006-2017 Microchip Technology Inc.

6.6

RX Data FIFO Direct PIO Burst Reads

In this mode the upper address inputs are not decoded, and any burst read of the LAN9220 will read the RX Data FIFO.

This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting

the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its

address when accessing the LAN9220. Timing is identical to a PIO Burst Read, and the FIFO_SEL signal has the same

timing characteristics as the address lines.

In this mode, performance is improved by allowing an unlimited number of back-to-back read cycles. RX Data FIFO

Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). When either or both of these

control signals go high, they must remain high for the period specified.

Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

Note 6-5

When VDDVARIO is 3.3V or 2.5V, the maximum Tdoff time is 7ns. When VDDVARIO is 1.8V, the

maximum Tdoff time is 9ns.

FIGURE 6-5:

RX DATA FIFO DIRECT PIO BURST READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-6:

RX DATA FIFO DIRECT PIO BURST READ CYCLE TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

165

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tadv

Address Stable to Data Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

Note 6-5

tdoh

Data Output Hold Time

Note:

An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle

ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any

order.

Data Bus

nCS, nRD

FIFO_SEL

A[2:1]

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