LAN9220 datasheet(122/142 Pages) MICROCHIP

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LAN9220

DS00002417A-page 122

 2006-2017 Microchip Technology Inc.

6.8

TX Data FIFO Direct PIO Writes

In this mode the upper address inputs are not decoded, and any write to the LAN9220 will write the TX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the

FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address

when accessing the LAN9220. Timing is identical to a PIO write, and the FIFO_SEL signal has the same timing char-

acteristics as the address lines.

FIGURE 6-7:

TX DATA FIFO DIRECT PIO WRITE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-8:

TX DATA FIFO DIRECT PIO WRITE TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Write Cycle Time

165

tcsl

nCS, nWR Assertion Time

tcsh

nCS, nWR Deassertion Time (see Note below)

133

tasu

Address, FIFO_SEL Setup to nCS, nWR Assertion

tah

Address, FIFO_SEL Hold Time

tdsu

Data Setup to nCS, nWR Deassertion

tdh

Data Hold Time

Note:

A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends

when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.

Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum.

Data Bus

nCS, nWR

FIFO_SEL

A[2:1]

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