CS5530A datasheet(169/259 Pages) NSC

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Index 8Bh

General Purpose Timer 2 Control Register (R/W)

Reset Value = 00h

Re-trigger General Purpose Timer 1 on Secondary Hard Disk Activity: 0 = Disable; 1 = Enable.

Any access to the secondary hard disk drive address range selected in F0 Index 93h[4] reloads GP Timer 1.

VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh). 0 = 1 ms; 1 = 32 µs.

General Purpose Timer 2 Shift: GP Timer 2 is treated as an 8-bit or 16-bit timer. 0 = 8-bit; 1 = 16-bit.

As an 8-bit timer, the count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah).

As a 16-bit timer, the value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become

zero, and this 16-bit value is used as the count for GP Timer 2.

General Purpose Timer 1 Shift: GP Timer 1 is treated as an 8-bit or 16-bit timer. 0 = 8-bit; 1 = 16-bit.

As an 8-bit timer, the count value is that loaded into GP Timer 1 Count Register (F0 Index 88h).

As a 16-bit timer, the value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become

zero, and this 16-bit value is used as the count for GP Timer 1.

Timebase for General Purpose Timer 2: Selects timebase for GP Timer 2 (F0 Index 8Ah). 0 = 1 sec; 1 = 1 msec.

Re-trigger General Purpose Timer 2 on GPIO7 Pin Transition: A configured transition on the GPIO7 pin reloads GP

Timer 2 (F0 Index 8Ah). 0 = Disable; 1 = Enable.

F0 Index 92h[7] selects whether a rising- or a falling-edge transition acts as a reload. For GPIO7 to work here, it must first be

configured as an input (F0 Index 90h[7] = 0).

1:0

Reserved: Set to 0.

Index 8Ch

IRQ Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

IRQ Speedup Timer Count: This register holds the load value for the IRQ speedup timer. It is loaded into the timer when

Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the event

occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expiration, no SMI

is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 ms.

This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical

value here would be 2 to 4 ms.

Index 8Dh

Video Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

Video Speedup Timer Count: This register holds the load value for the Video speedup timer. It is loaded into the timer

when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and any access to the graphics controller occurs. When a video

access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expira-

tion, no SMI is generated; the Suspend Modulation begins again. The video speedup timer’s timebase is 1 ms.

This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula-

tions. A typical value here would be 50 to 100 ms.

Index 8Eh

VGA Timer Count Register (R/W)

Reset Value = 00h

7:0

VGA Timer Load Value: This register holds the load value for the VGA timer. The value is loaded into the timer when the

timer is enabled (F0 Index 83h[3] = 1). The timer is decremented with each clock of the configured timebase (F0 Index

8Bh[6]). Upon expiration of the timer, an SMI is generated and the status is reported in F1BAR+Memory Offset 00h/02h[6]

(only). Once expired, this timer must be re-initialized by disabling it (F0 Index 83h[3] = 0) and then enabling it (F0 Index

83h[3] = 1). When the count value is changed in this register, the timer must be re-initialized in order for the new value to be

loaded.

This timer’s timebase is selectable as 1 ms (default) or 32 µs. (F0 Index 8Bh).

Note: Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. It is

not affected by the Global Power Management Enable setting at F0 Index 80h[0].

Index 8Fh

Reserved

Reset Value = xxh

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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