CS5530A datasheet(173/259 Pages) NSC

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Index 9Eh-9Fh

Keyboard / Mouse Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Keyboard / Mouse Idle Timer Count: The idle timer loaded from this register determines when the keyboard and mouse

are not in use so that the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity

for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value when-

ever an access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space

when a mouse is enabled on a serial port. The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[3] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[3].

Index A0h-A1h

User Defined Device 1 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 1 (UDEF1) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C0h (base address regis-

ter) and F0 Index CCh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[4] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

Index A2h-A3h

User Defined Device 2 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 2 (UDEF2) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF2 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C4h (base address regis-

ter) and F0 Index CDh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[5] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[5].

Index A4h-A5h

User Defined Device 3 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 3 (UDEF3) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF3 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C8h (base address regis-

ter) and F0 Index CEh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[6] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[6].

Index A6h-A7h

Video Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Video Idle Timer Count: The idle timer loaded from this register determines when the graphics subsystem has been idle as

part of the Suspend determination algorithm. The 16-bit value programmed here represents the period of video inactivity

after which the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the

graphics controller space. The timer uses a 1 second timebase.

In a GX-series processor based system the graphics controller is embedded in the CPU, so video activity is communicated

to the CS5530A via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530A also detects accesses

to standard VGA space on PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used.

To enable this timer set F0 Index 81h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[7].

Index A8h-A9h

Video Overflow Count Register (R/W)

Reset Value = 0000h

15:0

Video Overflow Count: Each time the Video Speedup timer (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the

100 ms timer expires before the Video Speedup timer lapses, the Video Overflow Count Register increments and the 100

ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count contained in this

Index AAh-ABh

Reserved

Reset Value = xxh

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 173 Page - National Semiconductor (TI)

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