CS5530A datasheet(175/259 Pages) NSC

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Index B8h

DMA Shadow Register (RO)

Reset Value = xxh

7:0

DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers. At

power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this reg-

ister resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to

that location.

The read sequence for this register is:

1. DMA Channel 0 Mode Register

2. DMA Channel 1 Mode Register

3. DMA Channel 2 Mode Register

4. DMA Channel 3 Mode Register

5. DMA Channel 4 Mode Register

6. DMA Channel 5 Mode Register

7. DMA Channel 6 Mode Register

8. DMA Channel 7 Mode Register

9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)

10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 ms, all other bits are 0)

Index B9h

PIC Shadow Register (RO)

Reset Value = xxh

7:0

PIC Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interrupt Con-

troller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it.

A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last

data written to that location.

The read sequence for this register is:

1. PIC1 ICW1

2. PIC1 ICW2

3. PIC1 ICW3

4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0

5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

7. PIC2 ICW1

8. PIC2 ICW2

9. PIC2 ICW3

10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0

11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register value,

then with the shadow register value ORed with C0h.

Index BAh

PIT Shadow Register (RO)

Reset Value = xxh

7:0

PIT Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interval Timer

registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write

to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data

written to that location.

The read sequence for this register is:

1. Counter 0 LSB (least significant byte)

2. Counter 0 MSB

3. Counter 1 LSB

4. Counter 1 MSB

5. Counter 2 LSB

6. Counter 2 MSB

7. Counter 0 Command Word

8. Counter 1 Command Word

9. Counter 2 Command Word

Note: The LSB/MSB of the count is the Counter base value, not the current value.

Bits [7:6] of the command words are not used.

Index BBh

RTC Index Shadow Register (RO)

Reset Value = xxh

7:0

RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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CS5530A Datasheet(PDF) 175 Page - National Semiconductor (TI)

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