CS5530A datasheet(174/259 Pages) NSC

174 / 259 page

www.national.com

174

Revision 1.1

Index ACh-ADh

Secondary Hard Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Secondary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the secondary

hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of second-

ary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value

whenever an access occurs to the configured secondary hard disk’s data port (configured in F0 Index 93h[4]). The timer

uses a 1 second timebase.

To enable this timer set F0 Index 83h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[4].

Index AEh

CPU Suspend Command Register (WO)

Reset Value = 00h

7:0

Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] =

0) and all SMI status bits are 0, a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU

in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt con-

dition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after

the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked,

allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the

only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI

source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake-

up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI

events are also Resume events.

Index AFh

Suspend Notebook Command Register (WO)

Reset Value = 00h

7:0

Software CPU Stop Clock Suspend (Write Only): A write to this register causes a SUSP#/SUSPA# handshake with the

CPU, placing the CPU in a low-power state. Following this handshake, the SUSP_3V pin is asserted. The SUSP_3V pin is

intended to be used to stop all system clocks.

Upon a Resume event (see Note), the SUSP_3V pin is deasserted. After a slight delay, the CS5530A deasserts the SUSP#

signal. Once the clocks are stable, the processor deasserts SUSPA# and system operation resumes.

Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the

only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI

source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake-

up the system from Suspend when the clocks are stopped.

Index B0h-B3h

Reserved

Reset Value = xxh

Index B4h

Floppy Port 3F2h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 3F2h Shadow (Read Only): Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B5h

Floppy Port 3F7h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 3F7h Shadow (Read Only): Last written value of I/O Port 3F7h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B6h

Floppy Port 1F2h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 1F2h Shadow (Read Only): Last written value of I/O Port 1F2h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B7h

Floppy Port 1F7h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 1F7h Shadow (Read Only): Last written value of I/O Port 1F7h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 174 Page - National Semiconductor (TI)

CS5530A Datasheet(HTML) 174 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL