CS5530A datasheet(170/259 Pages) NSC

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Revision 1.1

Index 90h

GPIO Pin Direction Register 1 (R/W)

Reset Value = 00h

GPIO7 Direction: Selects if GPIO7 is an input or output. 0 = Input; 1 = Output.

GPIO6 Direction: Selects if GPIO6 is an input or output. 0 = Input; 1 = Output.

GPIO5 Direction: Selects if GPIO5 is an input or output. 0 = Input; 1 = Output.

GPIO4 Direction: Selects if GPIO4 is an input or output. 0 = Input; 1 = Output.

GPIO3 Direction: Selects if GPIO3 is an input or output. 0 = Input; 1 = Output.

GPIO2 Direction: Selects if GPIO2 is an input or output. 0 = Input; 1 = Output.

GPIO1 Direction: Selects if GPIO1 is an input or output. 0 = Input; 1 = Output.

GPIO0 Direction: Selects if GPIO0 is an input or output. 0 = Input; 1 = Output.

Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins’ use as the

alternate function.

Index 91h

GPIO Pin Data Register 1 (R/W)

Reset Value = 00h

GPIO7 Data: Reflects the level of GPIO7. 0 = Low; 1 = High.

GPIO6 Data: Reflects the level of GPIO6. 0 = Low; 1 = High.

GPIO5 Data: Reflects the level of GPIO5. 0 = Low; 1 = High.

GPIO4 Data: Reflects the level of GPIO4. 0 = Low; 1 = High.

GPIO3 Data: Reflects the level of GPIO3. 0 = Low; 1 = High.

GPIO2 Data: Reflects the level of GPIO2. 0 = Low; 1 = High.

GPIO1 Data: Reflects the level of GPIO1. 0 = Low; 1 = High.

GPIO0 Data: Reflects the level of GPIO0. 0 = Low; 1 = High.

Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from

this register read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h.

Index 92h

GPIO Control Register 1 (R/W)

Reset Value = 00h

GPIO7 Edge Sense for Reload of General Purpose Timer 2: Selects which edge transition of GPIO7 causes

GP Timer 2 to reload. 0 = Rising; 1 = Falling (Note 2).

GPIO6 Enabled as Lid Switch: Allow GPIO6 to act as the lid switch input. 0 = GPIO6; 1 = Lid switch.

When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI.

The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[3].

If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid’s position.

GPIO2 Edge Sense for SMI: Selects which edge transition of the GPIO2 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 2 must be set to enable this bit.

GPIO1 Edge Sense for SMI: Selects which edge transition of the GPIO1 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 1 must be set to enable this bit.

GPIO0 Edge Sense for SMI: Selects which edge transition of the GPIO0 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 1 must be set to enable this bit.

Enable GPIO2 as an External SMI Source: Allow GPIO2 to be an external SMI source and generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable (Note 3).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 87h/F7h[7].

Enable GPIO1 as an External SMI Source: Allow GPIO1 to be an external SMI source and generate an SMI on either a

rising- or falling-edge transition (depends upon setting of bit 4). 0 = Disable; 1 = Enable (Note 3).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 87h/F7h[6].

Enable GPIO0 as an External SMI Source: Allow GPIO0 to be an external SMI source and generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 3). 0 = Disable; 1 = Enable (Note 3)

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 87h/F7h[5].

Notes: 1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h).

2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both.

3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the

system from Suspend when the clocks are stopped.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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