CS5530A datasheet(171/259 Pages) NSC

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Index 93h

Miscellaneous Device Control Register (R/W)

Reset Value = 00h

Floppy Drive Port Select: All system resources used to power manage the floppy drive use the primary or secondary FDC

addresses for decode. 0 = Primary; 1 = Primary and Secondary.

Reserved: This bit must always be set to 1.

Partial Primary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as primary hard disk

accesses.

0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h

1 = Power management monitors only writes to I/O Port 1F6h and 1F7h

Partial Secondary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as secondary hard

Disk accesses.

0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h

1 = Power management monitors only writes to I/O Port 176h and 177h

3:2

Reserved: Set to 0.

Mouse on Serial Enable: Mouse is present on a serial port. 0 = No; 1 = Yes. (Note)

Mouse Port Select: Selects which serial port the mouse is attached to. 0 = COM1; 1 = COM2. (Note)

Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to

monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a

mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen.

These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Paral-

lel/Serial Port Idle Timer Count Register (F0 Index 9Ch).

Index 94h

Suspend Modulation OFF Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Deasserted Count: This 8-bit value represents the number of 32 µs intervals that the SUSP# pin will be

deasserted to the GX-series processor. This timer, together with the Suspend Modulation ON Count Register (F0 Index

95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an

effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption.

This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

Index 95h

Suspend Modulation ON Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Asserted Count: This 8-bit value represents the number of 32 µs intervals that the SUSP# pin will be

asserted. This timer, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Mod-

ulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock fre-

quency, allowing the power manager to reduce CPU power consumption.

This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

Index 96h

Suspend Configuration Register (R/W)

Reset Value = 00h

7:5

Reserved: Set to 0.

Power Savings Mode: 0 = Enable; 1 = Disable.

Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included.

Suspend Mode Configuration: “Special 3 Volt Suspend” mode to support powering down a GX-series processor during

Suspend. 0 = Disable; 1 = Enable.

SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs.

0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI

occurs.

1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory

Offset 08h).

The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA

technology and power management operations occur at full speed. Two methods for accomplishing this are either to map

the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until

the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method.

The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect

if the Suspend Modulation feature is disabled (bit 0 = 0).

Suspend Modulation Feature: 0 = Disable; 1 = Enable.

When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation

OFF/ON Count Registers (F0 Index 94h/95h).

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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