CS5530A datasheet(176/259 Pages) NSC

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176

Revision 1.1

Index BCh

Clock Stop Control Register (R/W)

Reset Value = 00h

7:4

PLL Delay: The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the SUSP#

pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before starting execu-

tion. This delay is only invoked if the STP_CLK bit (bit 0) was set.

The four-bit field allows values from 0 to 15 ms.

0000 = 0 ms

0100 = 4 ms

1000 = 8 ms

1100 = 12 ms

0001 = 1 ms

0101 = 5 ms

1001 = 9 ms

1101 = 13 ms

0010 = 2 ms

0110 = 6 ms

1010 = 10 ms

1110 = 14 ms

0011 = 3 ms

0111 = 7 ms

1011 = 11 ms

1111 = 15 ms

3:1

Reserved: Set to 0.

CPU Clock Stop: 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.

Note: This register configures the CS5530A to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the

appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the

clock chip and CPU PLL to stabilize when an event Resumes the system.

A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as:

0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped. When a

break/resume event occurs, it releases the CPU halt condition.

1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU and

system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay programmed in bits [7:4]

will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Index BDh-BFh

Reserved

Reset Value = xxh

Index C0h-C3h

User Defined Device 1 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 1 (UDEF1) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).

Index C4h-C7h

User Defined Device 2 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 2 (UDEF2) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).

Index C8h-CBh

User Defined Device 3 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 3 (UDEF3) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).

Index CCh

User Defined Device 1 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped: User Defined Device 1 is: 0 = I/O; 1 = Memory.

6:0

Mask

If bit 7 = 0 (I/O):

Bit 6

0 = Disable write cycle tracking

1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking

1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (M/IO):

Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored.

Note: A “1” in a mask bit means that the address bit is ignored for comparison.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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