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CS5530A Datasheet(PDF) 232 Page - National Semiconductor (TI) |
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CS5530A Datasheet(HTML) 232 Page - National Semiconductor (TI) |
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232 / 259 page  www.national.com 232 Revision 1.1 Register Descriptions (Continued) 1 OEM_GPE_E01: Original Equipment Manufacturer General Purpose Event Enable Bit 1 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. 0 OEM_GPE_E00: Original Equipment Manufacturer General Purpose Event Enable Bit 0 - When set, enables a SCI to be generated when the corresponding GPE0_STS bit is set. ACPI_BASE 14h-17h SETUP_DATA — Setup Data Register (R/W) Reset Value = 00000000h During a read operation, SETUP_DATA returns the value of the internal setting specified by the current value in SETUP_IDX (ACPI_ABASE 0Eh-0Fh) ACPI_BASE 18h-1Fh Reserved Reset Value = 00h Reserved for future V-ACPI Implementations. Table 4-34. V-ACPI Registers (Continued) Bit Description Table 4-35. SETUP_IDX Values Index Operation 0x00 No operation 0x10 Configure GPIO0 to PM1A_STS or GPE0_STS bits 0x11 Configure GPIO1 to PM1A_STS or GPE0_STS bits 0x12 Configure GPIO2 to PM1A_STS or GPE0_STS bits 0x13 Configure GPIO3 to PM1A_STS or GPE0_STS bits 0x14 Configure GPIO4 to PM1A_STS or GPE0_STS bits 0x15 Configure GPIO5 to PM1A_STS or GPE0_STS bits 0x16 Configure GPIO6 to PM1A_STS or GPE0_STS bits 0x17 Configure GPIO7 to PM1A_STS or GPE0_STS bits 0x30 Configure IRQ0 to wakeup system 0x31 Configure IRQ1 to wakeup system 0x32 Do not use – Reserved for cascade interrupt 0x33 Configure IRQ3 to wakeup system 0x34 Configure IRQ4 to wakeup system 0x35 Configure IRQ5 to wakeup system 0x36 Configure IRQ6 to wakeup system 0x37 Configure IRQ7 to wakeup system 0x38 Configure IRQ8 to wakeup system (Defaults to RTC_STS in PM1A_STS) 0x39 Configure IRQ9 to wakeup system. 0x3A Configure IRQ10 to wakeup system. 0x3B Configure IRQ11 to wakeup system 0x3C Configure IRQ12 to wakeup system 0x3D Do not use – Reserved for math coprocessor 0x3E Configure IRQ14 to wakeup system 0x3F Configure IRQ15 to wakeup system 0x40 Generate GBL_STS – Sets the GLB_STS bit and generates a SCI to the OS 0x41 Configure IRQ to be used for SCI 0x42 Enable reads of ACPI registers 0x43 Do atomic I/O sequence 0x50 Video power 0x60 Soft SMI AX = 6000 emulation 0x61 Soft SMI AX = 6001 emulation 0x62 Soft SMI AX = 6002 emulation 0x63 Soft SMI AX = 6003 emulation 0x64 Audio power control |
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