CS5530A datasheet(233/259 Pages) NSC

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Table 4-36. GPIO Mapping (0x10-0x17)

SETUP_

DATA

Function

xx Value

0x00

No mapping – Do not use this GPIO pin

0x08

Assign GPIOx to PWRBTN_STS bit in PM1A_STS

0x09

Assign GPIOx to SLPBTN_STS in PM1A_STS

0x10

Assign GPIOx to bit 0 in GPE0_STS register

0x11

Assign GPIOx to bit 1 in GPE0_STS register

0x12

Assign GPIOx to bit 2 in GPE0_STS register

0x13

Assign GPIOx to bit 3 in GPE0_STS register

0x14

Assign GPIOx to bit 4 in GPE0_STS register

0x15

Assign GPIOx to bit 5 in GPE0_STS register

0x16

Assign GPIOx to bit 6 in GPE0_STS register

0x17

Assign GPIOx to bit 7 in GPE0_STS register

0x18

Assign GPIOx to bit 8 in GPE0_STS register

0x19

Assign GPIOx to bit 9 in GPE0_STS register

0x1A

Assign GPIOx to bit 10 in GPE0_STS register

0x1B

Assign GPIOx to bit 11 in GPE0_STS register

0x1C

Assign GPIOx to bit 12 in GPE0_STS register

0x1D

Assign GPIOx to bit 13 in GPE0_STS register

0x1E

Assign GPIOx to bit 14 in GPE0_STS register

0x1F

Assign GPIOx to bit 15 in GPE0_STS register

y Value (y values may be ORed together to get the desired combination of features)

0x01

Falling edge

0x02

Rising edge

0x04

Power button

0x08

Reserved

Note: For GPIO mapping, a value of 0000zyxx is used where:

z = a runtime/wake indicator

y = the edge to be used

xx = a bit in either PM1A_STS or GPE0_STS

When using V-ACPI both edges of GPIO6 can be sensed. When using the CS5530A, GPIO6 provides additional hardware that

enables the chipset to generate an SMI on both the rising and falling edges of the input signal.

CS5530A Datasheet(PDF) 233 Page - National Semiconductor (TI)

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