LTM2887 datasheet(17/38 Pages) LINER

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LTM2887

2887fb

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APPLICATIONS INFORMATION

Figure 5. Adjustable Voltage Rails

Isolated Supply Adjustable Operation

Thetwoisolatedpowerrailsmaybeadjustedbyconnection

of external resistive dividers. The unadjusted output volt-

agesrepresentthemaximumsforguaranteedperformance.

Figure 5 illustrates configuration of the output power rails

for VCC2 = 3.3V, and VL2 = 2.5V.

The output adjustment range for VCC2 is 0.6V to 5.5V.

Output voltage is calculated by:

VCC2 = 0.6V(1 + R2/R1)

Adjustment range for VL2 is 3V to 5.5V for the LTM2887-I,

and 1.8V to 5.5V for the LTM2887-S. Output voltage is

calculated by:

VL2 = 0.6V(1 + R5/R4)

The value of R1 or R4 should be no greater than 6.04k to

minimize errors in the output voltage caused by the adjust

pin bias currents and internal voltage dividers.

Operation at low output voltages may result in thermal

shutdown due to low dropout regulator power dissipation.

Isolated Supply Programmable Current Limit

The IVCC2 pin and IVL2 pin allow programming of the

maximum current available from VCC2 and VL2 respec-

tively. The current adjustments may be used to limit the

maximum output power, insuring that either voltage rail

does not collapse if the opposing rail is loaded beyond

its capability. The current limit threshold (ILIMIT) is set by

attaching a resistor (RIMAX) from IVCC2 or IVL2 to GND2:

RIMAX = [119.22-(0.894 • (VCC2, VL2))]/ILIMIT

The accuracy of this equation for setting the resistor value

is approximately ±1%. Unit values are amps, volts, and

ohms. Figure 5 shows the current limit programmed for

75mA on VCC2 and 25mA on VL2. If the external program-

mable current limit is not needed, the IVCC2 pin or IVL2

must be connected to GND2. The current limit pins are

internally decoupled with 10nF capacitors.

Channel Timing Uncertainty

Multiplechannelsaresupportedacrosstheisolationbound-

ary by encoding and decoding of the inputs and outputs.

Up to three signals in each direction are assembled as a

packet and transferred across the isolation barrier. The

time required to transfer all 3 bits is 100ns maximum,

and sets the limit for how often a signal can change on

the opposite side of the barrier. Encoding transmission is

independent for each data direction. The technique used

assigns SCK or SCL on the logic side, and SDO2 or I2 on

the isolated side, the highest priority such that there is

2887 F05

CS2

LTM2887-5S

VCC

GND

GND2

SDI

SDI2

DO2

SCK

SCK2

VL2

AVL2

IVL2

AVCC2

IVCC2

VCC2

SDO

SDO2

DO1

3.3V AT 75mA

2.5V AT 25mA

4.64k

19.1k

1.54k

6.04k

27.4k

6.04k

SDOE

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