Electronic Components Datasheet Search
  English  ▼

X  

OXCB950 Datasheet(PDF) 15 Page - List of Unclassifed Manufacturers

Part # OXCB950
Description  Integrated High Performance UART Cardbus / PCI interface
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC - List of Unclassifed Manufacturers

OXCB950 Datasheet(HTML) 15 Page - List of Unclassifed Manufacturers

Back Button OXCB950 Datasheet HTML 11Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 12Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 13Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 14Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 15Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 16Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 17Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 18Page - List of Unclassifed Manufacturers OXCB950 Datasheet HTML 19Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 68 page
background image
Data Sheet Revision 1.1
Page 15
OXCB950
OXFORD SEMICONDUCTOR LTD.
6.3
Accessing the UART function
Access to the internal UART is achieved via standard I/O and memory mapping, at addresses defined by the Base Address
Registers (BARs) in the PCI configuration space. These BARs are configured by the system to allocate blocks of I/O and
memory space to this logical function, according to the size required by the function. The base addresses that have been
allocated can then be used to access this uart function. The mapping of these BARs is shown in the table below.
BAR
UART Function
0
Internal UART (I/O Mapped)
1
Internal UART(Memory Mapped)
2
Local configuration registers (I/O Mapped)
3
Local configuration registers (Memory Mapped)
4
Cardbus Status Registers (Memory Mapped)
– relevant to cardbus mode only
5
Unused
Table 4: Base Address Register definition
6.3.1
Cardbus/PCI access to the internal UART
IO and memory space
BAR 0 and BAR 1 of function 0 are used to access the internal UART. The function reserves an 8-byte block of I/O space and a
4K byte block of memory space. Once the I/O and/or the Memory access enable bits in the Command register (of the PCI
configuration space) are set, the UART can be accessed following the mapping shown in Table 5.
UART
Address
Cardbus/PCI Offset from Base Address 0
for Function0 in IO space (hex)
(hex)
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
UART
Address
Cardbus/PCI Offset from Base Address 1
for Function0 in Memory space (hex)
000
00
001
04
002
08
003
0C
004
10
005
14
006
18
007
1C
Table 5: Cardbus/PCI address map for the internal UART (I/O and memory)
Note 1:
Since 4K of memory space is reserved and the full bus address is not used for decoding, there are a number of aliases of the UART in the allocated
memory region



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com