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TAS5086 Datasheet(PDF) 5 Page - Texas Instruments

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Part # TAS5086
Description  PurePath Digital AUDIO SIX-CHANNEL PWM PROCESSOR
PDF  33 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5086 Datasheet(HTML) 5 Page - Texas Instruments

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PHYSICAL CHARACTERISTICS
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VR_ANA
AVDD
AVSS
AVSS_GR
PLL_FLTM
PLL_FLTP
AVSS
MCLK
RESET
PDN
DVDD
DVSS
DVSS_OSC
OSC_RES
VR_OSC
MUTE
SDA
SCL
LRCLK
PWM_1
PWM_2
PWM_3
PWM_4
PWM_5
PWM_6
VALID2
VALID1
VR_DIG
DVSS_ESD
VREG_EN
BKND_ERR
SDIN1
SDIN2
SDIN3
SDIN4
SDOUT
RESERVED
SCLK
DBT PACKAGE
(TOP VIEW)
TAS5086
SLES131 – FEBRUARY 2005
TERMINAL FUNCTIONS
TERMINAL
5 V
I/O(1)
TERMINATION(2)
DESCRIPTION
TOLERANT
NO.
NAME
Voltage reference for analog supply 1.8 V. A pin-out of the internally
regulated 1.8-V power. A 0.1-µF low ESR capacitor should be connected
1
VR_ANA
P
between this terminal and AVSS_PLL. This terminal must not be used to
power external devices.
2
AVDD
P
3.3-V analog power supply
3
AVSS
P
Analog supply ground
4
AVSS_GR
P
Connection to guard ring
5
PLL_FLTM
AO
PLL negative input
6
PLL_FLTP
AI
PLL positive input
7
AVSS
P
Analog supply ground
MCLK is a 3.3-V clock master clock input. The input frequency of this
8
MCLK
DI
5V
Pulldown
clock can range from 4 MHz to 50 MHz.
A system reset is generated by applying a logic low to this terminal.
RESET is an asynchronous control signal that restores the TAS5086 to its
default conditions, sets the VALID2 output low, and places the PWM in the
9
RESET
DI
5V
Pullup
hard mute (M) state. Master Volume is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a 4-5
ms. device initialization and set the volume at mute.
(1)
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2)
All pullups are 20-µA weak pull-ups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA, while maintaining a logic ‘0’ drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA, while maintaining a logic 1 drive level.
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