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VOLUME CONTROL REGISTER (0x0E)

MODULATION LIMIT REGISTER (0x10)

PWM START REGISTER (0X18)

TAS5086

SLES131 – FEBRUARY 2005

Bit D7: Reserved = 1

Bit D6: If 0 then Biquad 1 (BQ1) Volume Compensation part only is disabled (default)

If 1 then BQ1 Volume Compensation is enabled

Bit D5: If 0 Disable 38-kHz detection (38 kHz should be set manually by micro)

If 1 Enable 38-kHz detection

Bit D4: Reserved = 1

Bit D3: Not Used

Bit D2–D0: Volume slew rate

Table 9. Volume Control Register

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

1

–

–

–

–

–

–

–

Reserved (Must be 1)

–

0

–

–

–

–

–

–

Disable Biquad Volume Compensation

–

1

–

–

–

–

–

–

Enable Biquad Volume Compensation

–

–

1

–

–

–

–

–

Reserved = 1

–

–

–

1

–

–

–

–

Reserved (Must be 1)

Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.

Table 10. Modulation Limit Unit

D7

D6

D5

D4

D3

D2

D1

D0

LIMIT

MIN WIDTH

MODULATION

[DCLKs]

[DCLKs]

LIMIT

–

–

–

–

–

0

0

0

1

2

99.2%

–

–

–

–

–

0

0

1

2

4

98.4%

–

–

–

–

–

0

1

0

3

6

97.7%

–

–

–

–

–

0

1

1

4

8

96.9%

–

–

–

–

–

1

0

0

5

10

96.1%

–

–

–

–

–

1

0

1

6

12

95.3%

–

–

–

–

–

1

1

0

7

14

94.5%

–

–

–

–

–

1

1

1

8

16

93.8%

Bit D7 and D6 should always be set to 0.

Bits D5-D0: Define which PWM’s will be used for charging the split caps and which PWM’s should stay low to for

the output stages to be held in hi-Z under split capacitor charging.

For most systems this register is always 0X3F. The setting depends on how the back-end is connected.

Table 11. PWM Start Register

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

0

–

–

–

–

–

–

–

Reserved = 0

–

0

–

–

–

–

–

–

Reserved = 0

–

–

1

–

–

–

–

–

Start channel 6 under part 1 of the start

–

–

0

–

–

–

–

–

Start channel 6 under part 2 of the start

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