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CLOCK CONTROL REGISTER (0x00)

TAS5086

SLES131 – FEBRUARY 2005

SERIAL CONTROL INTERFACE REGISTER SUMMARY (continued)

SUB-ADDRESS

REGISTER NAME

NO. OF

CONTENTS

INITIALIZATION VALUE

(0xSS)

BYTES

0x19

Surround Register

1

Description shown in subsequent section

00

0x1A

Split Cap Charge Period Regis-

1

Description shown in subsequent section

18

ter

0x1B

OSC_TRIM

1

Oscillator Trim Register

82

0X1C

BKNDERR Register

1

BKNDErr Register

05

0x1D–0x1F

0x20

Input MUX Register

4

Description shown in subsequent section

0x00 0x01 0x23 0x45

0x21

Downmix Input MUX Register

4

Description shown in subsequent section

0x00 0x00 0x00 0x3F

0x22

Am Tuned Frequency

4

Description shown in subsequent section

0x00 0x00 0x00 0x00

0X23

ch6_bq[1]

20

b0 (25:24) b0(23:16), b0(15:8), b0(7:0)

0x00, 0x80, 0x00,0x00

b1 (25:24) b1(23:16), b1(15:8), b1(7:0)

0x00, 0x00, 0x00,0x00

b2 (25:24) b2(23:16), b2(15:8), b2(7:0)

0x00, 0x00, 0x00,0x00

a1 (25:24) a1(23:16), a1(15:8), a1(7:0)

0x00, 0x00, 0x00,0x00

A2 (25:24) a2(23:16), a2(15:8), a2(7:0)

0x00, 0x00, 0x00,0x00

0X24

ch6_bq[2]

20

b0 (25:24) b0(23:16), b0(15:8), b0(7:0)

0x00, 0x80, 0x00,0x00

b1 (25:24) b1(23:16), b1(15:8), b1(7:0)

0x00, 0x00, 0x00,0x00

b2 (25:24) b2(23:16), b2(15:8), b2(7:0)

0x00, 0x00, 0x00,0x00

a1 (25:24) a1(23:16), a1(15:8), a1(7:0)

0x00, 0x00, 0x00,0x00

A2 (25:24) a2(23:16), a2(15:8), a2(7:0)

0x00, 0x00, 0x00,0x00

0x25

PWM Mux Register

Shown in Subsection section

0x00, 0x32, 0x45, 0x10,

0x26

1/G Register

4

x (25:24) x(23:16), x(15:8), x(7:0)

0x00, 0x80, 0x00,0x00

0x27

0x28

Scale Register

4

x (25:24) x(23:16), x(15:8), x(7:0)

0x00, 0x80, 0x00,0x00

0x29–0xFD

0XFE

Repeat Subaddress

4+4N

0x00,0x00,0x00,0x00

0xFF

(2)

Reserved registers should not be accessed.

In the manual mode, the clock control register provides a way for the system micro to update the data and clock

rates based on the sample rate and associated clock frequencies. In the auto detect mode, the clocks are

automatically determined by the TAS5086. In this case, the clock control register contains the auto-detected

clock status as automatically detected. Bits D7–D5 selects the sample rate. Bits D4–D2 selects the MCLK

frequency. Bit D1 selects the bit clock (SCLK) frequency. Bit D0 is used in manual mode only. In this mode,

when the clocks are updated a 1 must be written to D1 to inform the TAS5086 that the written clocks are valid.

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

0

0

0

–

–

–

–

–

Fs = 32-kHz sample rate

0

0

1

–

–

–

–

–

Fs = 38-kHz sample rate

0

1

0

–

–

–

–

–

Fs = 44.1-kHz sample rate

0

1

1

–

–

–

–

–

Fs = 48-kHz sample rate

1

0

0

–

–

–

–

–

Fs = 88.2- kHz sample rate

1

0

1

–

–

–

–

–

Fs = 96-kHz sample rate

1

1

0

–

–

–

–

–

Fs = 176.4-kHz sample rate

1

1

1

–

–

–

–

–

Fs = 192-kHz sample rate

(1)

Default values are in bold

18