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DESCRIPTION (CONTINUED)

Serial

Data

Interface

Serial

Control

Interface

System

Control

Chan.

1 − 6

1− 5

Down

Mix

SDIN1

SDIN2

SDIN3

SDIN4

SDA

SCL

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

VALID1

Power

Supply

DVDD

DVSS

DVSS_ESD

VR_DIG

VR_ANA

VR_OSC

AVDD

AVSS_PLL

SDOUT

Clock Rate

/ Error

Detection

and PLL

MCLK

SCLK

LRCLK

PLLFLTP

PLLFLTM

HFCLK

OSCFLT

OSC_RES

1 LF

2 RF

3 LS

4 RS

5 C

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX

1− 6

I2S Serial

Output

MUX

L’

R’

L’

R’

(L’+R’) / 2

VALID2

1 − 5

Channel

Selector

Block

Channel Six Processing

Bass Management

(L’+R’)/2

MUX

MUX

PWM

Vol

Ch

1−6

6

6

6

6

6

6

SDIN4

SDIN4

Downmix

PWM

Control

PDN

RESET

MUTE

VREG_EN

BKNDERR

TAS5086

SLES131 – FEBRUARY 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The TAS5086 accepts a 64-Fs bit clock for all data rates. The TAS5086 can also accept a 48 Fs SCLK rate for

MCLK ratios of 192 Fs and 384 Fs.

The TAS5086 is composed of five functional blocks.

1. Power Supply

2. Clock, PLL, and Serial Data Interface

3. Serial Control Interface

4. Device Control

5. PWM Section

Figure 1 shows the functional structure of the TAS5086.

Figure 1. TAS5086 Functional Block Diagram

2