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TAS5086 Datasheet(PDF) 25 Page - Texas Instruments

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Part # TAS5086
Description  PurePath Digital AUDIO SIX-CHANNEL PWM PROCESSOR
PDF  33 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5086 Datasheet(HTML) 25 Page - Texas Instruments

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BKNDERR REGISTER (0x1C)
TAS5086
SLES131 – FEBRUARY 2005
2. Write data 0x6D to register 0x00
3. Write data 0x01 to register 0x1B
4. Read and save data from register 0x27 = 0xH7H6H5H4H3H2H1H0
Where,
H7H6H5H4 = Factory Trim Value
H3H2 H1H0 = Location to Write Factory Trim
5. Continually read register 0x27 until H3H2 and H1H0 are non-zero
6. Write data 0xA5 A5 A5 A5 to register 0xF8
7. Write data 0x00 06 00 EF to register 0xC9
8. Write data 0x00 00 00 00
0x00 00 00 H5H4 to register 0xCA
9. Write data 0x00 06 00 F1 to register 0xC9
10. Write data 0x00 00 00 00
0x00 00 00 H7H6 to register 0xCA
Table 14. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
–
0
–
–
–
–
–
–
Oscillator Trim Not Done (Read Only)
–
1
–
–
–
–
–
–
Oscillator Trim Done
–
–
0
0
0
0
–
–
Reserved
–
–
–
–
–
–
0
–
Select Factory Trim
–
–
–
–
–
–
1
–
Select Field Trim
–
–
–
–
–
–
–
1
Trim Oscillator Command
When a back-end error signal is received, all the output stages are reset by setting all PWM, Valid1, and Valid2
signals low. Hereafter, the modulator waits for approximately the time indicated in the table before it starts.
Table 15. BKNDERR Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
–
–
–
–
0
0
0
0
Set back end reset period < 1.3 ms
–
–
–
–
0
0
0
1
Set back end reset period 1.3 ms
–
–
–
–
0
0
1
0
Set back end reset period 2.6 ms
–
–
–
–
0
0
1
1
Set back end reset period 3.9 ms
–
–
–
–
0
1
0
0
Set back end reset period 5.2 ms
–
–
–
–
0
1
0
1
Set back end reset period 6.5 ms
–
–
–
–
0
1
1
0
Set back end reset period 7.8 ms
–
–
–
–
0
1
1
1
Set back end reset period 9.1 ms
–
–
–
–
1
0
0
0
Set back end reset period 10.4 ms
–
–
–
–
1
0
0
1
Set back end reset period 11.7 ms
–
–
–
–
1
0
1
0
Set back end reset period 13 ms
–
–
–
–
1
0
1
1
Set back end reset period 13 ms
–
–
–
–
1
1
X
X
Set back end reset period 13 ms
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