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DEVICE ID REGISTER (0X01)

ERROR STATUS REGISTER (0x02)

SYSTEM CONTROL REGISTER 1 (0X03)

TAS5086

SLES131 – FEBRUARY 2005

Table 1. Clock Control Register (continued)

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

–

–

–

0

0

0

–

–

–

–

–

0

0

1

–

–

MCLK frequency = 128 x Fs

–

–

–

0

1

0

–

–

MCLK frequency = 192 x Fs

–

–

–

0

1

1

–

–

MCLK frequency = 256 x Fs

–

–

–

1

0

0

–

–

MCLK frequency = 384 x Fs

–

–

–

1

0

1

–

–

MCLK frequency = 512 x Fs

–

–

–

1

1

0

–

–

Reserved

–

–

–

1

1

1

–

–

Reserved

–

–

–

–

–

–

1

–

Bit clock (SCLK) frequency = 48 x Fs

–

–

–

–

–

–

0

–

Bit clock (SCLK) frequency = 64 x Fs

–

–

–

–

–

–

–

0

Clock not valid (in manual mode only)

–

–

–

–

–

–

–

1

Clock valid iIn manual mode only)

(2)

Rate not available for 32-, 44.1-, 48-, 88.2-, and 96-kHz data rates

The device ID register contains the ID code for the TAS5086.

Table 2. General Status Register (x01)

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

0

Default

–

0

0

0

0

0

1

1

Identification code for the TAS5086

Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must

clear the register (write zeroes) and then read them to determine if there are any persistent errors.

Table 3. ErrorStatus Register (x02)

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

–

1

–

–

–

–

–

–

PLL auto lock error

–

–

1

–

–

–

–

–

SCLK error

–

–

–

1

–

–

–

–

LRCLK error

–

–

–

–

1

–

–

–

Frame slip

–

0

0

0

0

0

0

0

No errors

System Control Register 1 has several functions:

Bit D7: If 0 the dc-blocking filter for each channel is disabled

If 1 the dc-blocking filter (-3 dB cutoff < 1 Hz) for each channel is enabled (default)

Bit D6: Not used

Bit D5: If 0 use soft unmute on recovery from clock error. This is a slow recovery.

If 1 use hard unmute on recovery from clock error (default). This is a fast recovery.

Bit D4: If 0 the down mix is output on SDOUT as I2S signal (default)

If 1 SDIN4 is output on SDOUT as I2S signal

Bit D3: If 0 Clock Auto Detect is enabled (default)

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