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DETAILED DESCRIPTION

POWER SUPPLY

CLOCK, ERROR RATE DETECTION, AND PLL

SERIAL DATA INTERFACE

I

TAS5086

SLES131 – FEBRUARY 2005

The TAS5086 power supply section contains regulators that provide analog and digital regulated power for

various sections of the TAS5086. The analog supply supports the analog PLL while digital supplies support the

digital PLL, the digital audio processor, the pulse width modulator, and the output control (reclocker). The power

supply section is enabled via /VREG_EN.

This module provides the timing and serial data interface for the TAS5086.

The TAS5086 is a clock slave only device. It accepts MCLK, SCLK, and LRCLK.

The TAS5086 supports 64 Fs MCLK for the 176.4-kHz and 192-kHz data rates.

The TAS5086 accepts a 64 Fs SCLK rate for all MCLK ratios and a 48 Fs SCLK rate for MCLK ratios of 192

Fs and 384 Fs.

TAS5086 checks to verify that the SCLK is a specific value of 64 Fs or 48 Fs.

The TAS5086 supports a 1

× Fs LRCLK

The timing relationship of these clocks to SDIN1-4 and SDOUT are shown in subsequent sections.

The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to derive all

internal to produce a 196-MHz PLL output.

The TAS5086 can auto-detect and set the internal clock control logic to the appropriate settings for the

frequencies of 32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed

(176.4 kHz and 192 kHz). The automatic sample rate detection can be disabled and the values set via I

The TAS5086 also supports a AM interference avoidance mode during which the clock rate is adjusted, in

concert with the PWM sample rate converter to produce an PWM output at 7

×Fs, 8×Fs, or 9×Fs.

The sample rate must be set manually set during AM interference avoidance and when de-emphasis is enabled.

The TAS5086 uses an internal oscillator time base to provide reference timing information for the following:

MCLK, SCLK and LRCLK error detection

Permit I

Automatic data rate detection and setting (32 kHz, normal, double, and quad speed)

Automatic MCLK rate detection and setting (64, 128, 192, 256, 384, and 512 Fs)

Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The PWM outputs and down mix are derived from

SDIN1, SDIN2, and SDIN3. SDIN4 is a selectable pass-through signal that is available at SDOUT as an I

output. The TAS5086 accepts 32, 44.1, 48, 88.2, 96, 176.4, and 192-kHz serial data in 16-, 20-, or 24-bit data in

left, right, and I

Serial Data is output on SDOUT. The SDOUT data format is I

SDOUT output is synchronized to use the SCLK and LRCLK signals. There is a 1 to 2.5 LRCLK frame delay

from the input data to the output data depending upon the input serial data format. The SDOUT output has no

I

The parameters of this clock and serial data interface input format are I

The TAS5086 has an I

control interface supports both normal speed (100 kHz) and high speed (400 kHz) operations without wait states.

As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single byte and multi-byte read and write operations for status registers

and the general control registers associated with the PWM.

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