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SINGLE BYTE READ

SS

A5

A6

A1

A0 R/W ACK

A7

A6

A1

A0 ACK

D7

Start

Condition

Stop

Condition

Acknowledge

SS

SS

D0

ACK

Not

Acknowledge

SS

A5

A6

A1

A0

R/W ACK

Repeat

Start

Condition

Acknowledge

Acknowledge

Sub Address

Read/Write Bit

Read/Write Bit

Data Byte

MULTIPLE BYTE READ

SS

A6

A0

R/W ACK

A7

A0

ACK

D7

Start

Condition

Stop

Condition

Acknowledge

SS

ACK

Not

Acknowledge

SS

A6

A0

R/W ACK

Repeat

Start

Condition

Acknowledge

Acknowledge

ACK

D7

SS

D0 ACK

D7

SS

D0

Acknowledge

Acknowledge

Sub Address

and Read/Write Bit

and Read/Write Bit

Last

Data Byte

Other

Data Byte

COMMAND CHARACTERISTICS

TAS5086

SLES131 – FEBRUARY 2005

I

2. At a later time one or more append data transfers are performed to incrementally transfer the remaining

number of bytes in sequential order to complete the register write operation. Each of these append

operations is composed of the device address, write bit, append subaddress (0

×FE), an integer number of

four bytes of data followed by a stop condition.

3. The operation is terminated due to an error condition and the data is flushed - IF

–

If a new subaddress is written to the TAS5086 before the correct number of bytes has been written.

–

If a noninteger number of 4 bytes are written at the beginning or during any of the append operations.

–

If a read bit is sent.

As shown in Figure 13, a single byte data read transfer begins with the master device transmitting a start

condition followed by the I

followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal

memory address to be read. As a result, the read/write bit is set to a 0. After receiving the TAS5086 address and

the read/write bit, the TAS5086 responds with an acknowledge bit. In addition, after sending the internal memory

address byte or bytes, the master device transmits another start condition followed by the TAS5086 address and

the read/write bit again. This time the read/write bit is set to a 1 indicating a read transfer. After receiving the

TAS5086 and the read/write bit the TAS5086 again responds with an acknowledge bit. Next, the TAS5086

transmits the data byte from the memory address being read. After receiving the data byte, the master device

transmits a not-acknowledge followed by a stop condition to complete the single byte data read transfer.

Figure 13. Single Byte Read Transfer

A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes

are transmitted by the TAS5086 to the master device as shown in Figure 14. Except for the last data byte, the

master device responds with an acknowledge bit after receiving each data byte.

Figure 14. Multiple Byte Read Transfe

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