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SPLIT CAPACITOR CHARGE PERIOD REGISTER (0x1A)

OSCILLATOR TRIM REGISTER (0x1B)

TAS5086

SLES131 – FEBRUARY 2005

This register should contain the code that closely matches the external single-ended split capacitor charge

period. The TAS5086 waits for this period of time before starting the PWM signals. This helps reduce pops and

clicks. This is only used with the split-cap configuration.

Table 13. Split Capacitor Charge Period Register

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

–

–

–

0

0

–

–

–

No split capacitor charge period

–

–

–

0

1

0

0

0

13-ms split capacitor charge period

–

–

–

0

1

0

0

1

16.9-ms split capacitor charge period

–

–

–

0

1

0

1

0

23.4-ms split capacitor charge period

–

–

–

0

1

0

1

1

31.2-ms split capacitor charge period

–

–

–

0

1

1

0

0

41.6-ms split capacitor charge period

–

–

–

0

1

1

0

1

54.6-ms split capacitor charge period

–

–

–

0

1

1

1

0

72.8-ms split capacitor charge period

–

–

–

0

1

1

1

1

96.2-ms split capacitor charge period

–

–

–

1

0

0

0

0

130-ms split capacitor charge period

–

–

–

1

0

0

0

1

156-ms split capacitor charge period

–

–

–

1

0

0

1

0

234-ms split capacitor charge period

–

–

–

1

0

0

1

1

312-ms split capacitor charge period

–

–

–

1

0

1

0

0

416-ms split capacitor charge period

–

–

–

1

0

1

0

1

546-ms split capacitor charge period

–

–

–

1

0

1

1

0

728-ms split capacitor charge period

–

–

–

1

0

1

1

1

962-ms split capacitor charge period

–

–

–

1

1

0

0

0

1300-ms split capacitor charge period

–

–

–

1

1

0

0

1

1690-ms split capacitor charge period

–

–

–

1

1

0

1

0

2340-ms split capacitor charge period

–

–

–

1

1

0

1

1

3120-ms split capacitor charge period

–

–

–

1

1

1

0

0

4160-ms split capacitor charge period

–

–

–

1

1

1

0

1

5460-ms split capacitor charge period

–

–

–

1

1

1

1

0

7280-ms split capacitor charge period

–

–

–

1

1

1

1

1

9620-ms split capacitor charge period

The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost since

an external reference is not required. Currently, we recommend a trim resistor value of 18.2 k

Ω (1%). This

should be connected between TAS5086 pin 14 (OSC_RES) and pin 12 (DVSS).

There are two procedures available for trimming the internal oscillator. The Field Trim procedure #1

(recommended) requires that the LRCLK frequency be pre-determined whereas the Field Trim procedure #2

does not require that the LRCLK frequency is known.

Note that only one trim procedure should be used. It should always be run following RESET of the TAS5086.

Oscillator Field Trim Procedure #1 (Recommended if LRCLK Frequency is Known):

1. Reset the TAS5086 (power-up or toggle reset pin).

2. Provide a known LRCLK (e.g. 48 kHz)

3. Write LRCLK frequency to register 0x00 (e.g. for 48 kHz write 0x6D to register 0x00)

4. Write data 0x03 to register 0x1B

Oscillator Field Trim Procedure #2 (LRCLK Frequency is Not Known):

1. Reset the TAS5086 (power-up or toggle reset pin).

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