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TAS5086

SLES131 – FEBRUARY 2005

PHYSICAL CHARACTERISTICS (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

5 V

DESCRIPTION

TOLERANT

NO.

NAME

Power down, active low. PDN powers down all logic and stops all clocks

and performs a soft stop whenever a logic low is applied. The internal

parameters are preserved through a power down cycle, as long as a

10

PDN

DI

5V

Pullup

RESET is not active. The duration for system recovery from power down

is 100 ms. When released the PDN powers up all logic, starts all clocks,

and performs a soft start that returns to the previous configuration.

11

DVDD

P

3.3-V digital power supply

12

DVSS

P

Digital ground

13

DVSS_OSC

P

Digital ground for oscillator

14

OSC_RES 1

AO

Oscillator trim resistor

Voltage reference for analog supply 1.8 V. A pin-out of the internally

15

VR_OSC

P

ted between this terminal and AVSS_PLL. This terminal must not be used

to power external devices.

Performs a soft mute of outputs, active low (muted signal = a logic low,

normal operation = a logic high) The mute control provides a noiseless

16

/MUTE

DI

5V

Pullup

volume ramp to silence. Releasing mute provides a noiseless ramp to

previous volume.

17

SDA

DIO

5V

18

SCL

DI

5V

19

LRCLK

DI

5V

Pulldown

Input serial audio data left/right clock (sampling rate clock)

Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP)

20

SCLK

DIO

5V

Pulldown

input data bit clock that is supplied to the serial bit clock to other I2S bus.

21

RESERVED

RESERVED

Serial audio data 1 output is the only serial data output port. SDOUT

22

SDOUT

DI

supports I2S format only. SDOUT pin is used as input pin for selecting

OSC bypass mode.

Serial audio data 4 input is one of the serial data input ports. SDIN4

23

SDIN4

DI

Pulldown

supports four discrete (stereo) data formats

Serial audio data 3 input is one of the serial data input ports. SDIN3

24

SDIN3

DI

Pulldown

supports four discrete (stereo) data formats.

Serial audio data 2 input is one of the serial data input ports. SDIN2

25

SDIN2

DI

Pulldown

supports four discrete (stereo) data formats.

Serial audio data 1 input is one of the serial data input ports. SDIN1

26

SDIN1

DI

Pulldown

supports four discrete (stereo) data formats.

Active low. A backend error sequence is generated by applying logic LOW

27

BKND_ERR

DI

Pullup

to this terminal. The BKND_ERR results in all system parameters

unaffected while VALID2 goes low.

Voltage regulator enable. When enabled – low this input causes the power

28

VREG_EN

P

supply regulators to be enabled.

29

DVSS_ESD

P

ESD pin for digital supply

Voltage reference for digital PWM core supply 1.8 V. A pin-out of the

internally regulated 1.8-V power used by digital PWM core logic. A 0.1-µF

30

VR_DIG

P

DVSS_PWM. This terminal must not be used to power external devices

31

VALID2

DIO

Output indicating validity of PWM outputs - active high.

Soft start valid - Output indicating validity of soft start PWM output - active

32

VALID1

DO

high.

(3)

If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

(4)

If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

6