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SERIAL INTERFACE CONTROL AND TIMING

I

LRCLK (Note Reversed Phase)

SCLK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Left Channel

Right Channel

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSB

MSB

MSB

LSB

NOTE: All data presented in 2’s complement form with MSB first.

24-Bit Mode

20-Bit Mode

16-Bit Mode

32 clks

32 clks

2-Channel I2S (Phillips Format) Stereo Input

22

21 20

19

18

17 16 15

14

13 12

11

10

9

8

7

6

5

4

3

2

1

0

19 18

17

16

15

14

13

12 11

10

9

8

7

6

5

4

3

2

1

0

22

21 20

19

18

17 16 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

19

18

17

16 15

14

13 12 11

10

9

8

7

6

5

4

3

2

1

0

LRCLK

SCLK

Left Channel

Right Channel

15 14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13 12 11

10

9

8

7

6

5

4

3

2

1

0

LSB

MSB

MSB

LSB

NOTE: All data presented in 2’s complement form with MSB first.

23

23

24 clks

24 clks

24-Bit Mode

20-Bit Mode

16-Bit Mode

2-Channel I2S (Phillips Format) Stereo Input (24-Bit Transfer Word Size)

LEFT JUSTIFIED

TAS5086

SLES131 – FEBRUARY 2005

I

right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at 64

× Fs

is used to clock in the data. There is a delay of one bit clock from the time the L/RCLK signal changes state to

the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The

TAS5086 masks unused trailing data bit positions.

Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and

when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock

running at 64

× Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the

L/RCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5086 masks

unused trailing data bit positions.

11