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GENERAL I

SINGLE AND MULTIPLE BYTE TRANSFERS

TAS5086

SLES131 – FEBRUARY 2005

I

The I

system. Data is transferred on the bus serially one bit at a time. The address and data be transferred in byte

(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and stop

conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal

data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 10.

The master generate the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then wait for an acknowledge condition. The TAS5086 holds SDA low during acknowledge clock

period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence.

Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the

same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for

the SDA and SCL signals to set the HIGH level for the bus.

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 10.

The 7-bit address for the TAS5086 is 0011011.

The serial control interface supports both single byte and multi-byte read/write operations for status registers and

the general control registers associated with the PWM. However, for the DAP data processing registers, the

serial control interface supports only multiple byte (4 byte) read/write operations.

During multiple byte read operations, the TAS5086 responds with data, a byte at a time, starting at the

subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular

subaddress does not contain 32 bits, the unused bits are read as logic 0.

During multiple byte write operations, the TAS5086 compares the number of bytes transmitted to the number of

bytes that are required for each specific sub address. If a write command is received for a biquad subaddress,

the TAS5086 expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when

a stop command (or another start command) is received, the data received is discarded. Similarly, if a write

command is received for a mixer coefficient, the TAS5086 expects to receive one 32-bit word.

Supplying a subaddress for each subaddress transaction is referred to as random I

also supports sequential I

that subaddress and the fifteen subaddresses that follow, a sequential I

the data for all 16 subaddresses is successfully received by the TAS5086. For I

the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop

or start is transmitted, determines how many subaddresses are written. As was true for random addressing,

sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to

the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;

just the incomplete data is discarded.

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