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LRCLK

SCLK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

20 bit Mode

24 Bit Mode

Left Channel

Right Channel

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

16 Bit Mode

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSB

MSB

MSB

LSB

NOTE: All data presented in 2’s complement form with MSB first.

2-Channel Right-Justified (Sony Format) Stereo Input

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LRCLK

SCLK

20 Bit Mode

24 Bit Mode

Left Channel

Right Channel

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

16 Bit Mode

LSB

MSB

MSB

LSB

NOTE: All data presented in 2’s complement form with MSB first.

24 clks

24 clks

2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size)

I

TAS5086

SLES131 – FEBRUARY 2005

SERIAL INTERFACE CONTROL AND TIMING (continued)

Figure 8. Right Justified 64 Fs Format

Figure 9. Right Justified 48 Fs Bit Format

The TAS5086 has a bidirectional I

both 100 KBPS and 400 KBPS data transfer rates for single and multiple byte write and read operations. The

control interface is used to program the registers of the device and to read device status.

The TAS5086 supports wait state insertions by other I

I

The TAS5086 supports the standard-mode I

(400 kHz maximum).

13