DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
33
Version: DM9801-DS-P02
March 20, 2000
Noise Control B Register - Register 26
Bit
Bit Name
Default
Description
26.15 -
26.8
NSE_EVENTS
0x00, RW
Noise Events:
An 8 bit counter that records the number of noise events detected.
Overflows are held as 0xFF. This register is cleared by setting bit 6 of
the Control register (CLR_NS_EVNT).
26.7 -
26.0
NSE_ATTACK
0xF4, RW
Noise Attack:
Sets the attack characteristics of the noise algorithm. The high nibble
sets the number of noise events needed to raise the NOISE_LEVEL
immediately, while the low nibble is the number of noise events needed
to raise the NOISE_LEVEL at the end of an 870 msec period.
Aid Address Register - Register 27
Bit
Bit Name
Default
Description
27.15 -
27.2
Reserved
0, RW
Reserved:
These bits will always be read as 0.
27.1
DIS_LNK
0, RW
Disable Link:
This bit disables link integrity feature.
27.0
FWENA
0, RW
Four Wire Enable:
When read this bit will indicate the status of FWENA (pin 57) as read
during power up. If the FWENA pin status is 1 on power up, this bit can
be written to change the FWENA status. If the FWENA pin status is 0
on power up, writes to this bit are ignored.
Aid Address Register - Register 28
Bit
Bit Name
Default
Description
28.15 -
28.8
Reserved
0x00, RW
Reserved:
These bits will always be read as 0.
28.7 -
28.0
AID_ADDRESS
0x00, RW
AID Address:
Unless bit 7 of the Control register is set, the DM9801 is assured to
select a unique AID Address.
Addresses above 0xEF are reserved. Address 0xFF is defined to
indicate a Remote Command.
Aid Control Register - Register 29
Bit
Bit Name
Default
Description
29.15 -
29.8
AID_ISBI
0x40, RW
AID Inter Symbol Blanking Interval:
This value defines the number of TCLKs (116.7ns) between AID
pulses for symbol 0.
29.7 -
29.0
AID_INTERVAL
0x14, RW
AID Interval:
This value defines the number of TCLKs (116.7ns) separating AID
symbols.
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