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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
52
Preliminary
Version: DM9801-DS-P02
March 20, 2000
AC Electrical Characteristics (Over full range of operating condition unless specified otherwise)
Analog Transmitter Timing Diagram
HN+/-
tPW
tPWL
tPWH
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Transmitter (Analog)
tPW
Pulse Width
133
ns
tPWH
Pulse Width High
67
ns
tPWL
Pulse Width Low
67
ns
tPWH
OSC Pulse Width High
25
ns
tPWL
OSC Pulse Width Low
25
ns
MII (Media-Independent Interface) Clock Timing
Idle (excluding IFG time)
tPWH
TX_CLK/RX_CLK Pulse Width
High
1168
ns
tPWL
TX_CLK/RX_CLK Pulse Width
Low
1165
ns
Preamble (first 64 bits of TX MAC frame)
tTPWH
TX_CLK Pulse Width High
468
ns
tTPWL
TX_CLK Pulse Width Low
466
ns
tRPWH
RX_CLK Pulse Width High
-
ns
tRPWL
RX_CLK Pulse Width Low
-
ns
Data (throughout the data phase)
tPWH
TX_CLK/RX_CLK Pulse Width
High
468
ns
3us
5.6us
tPWL
TX_CLK/RX_CLK Pulse Width
Low
466
ns
3us
23us
IFG (88 bit times following CRS falling edge)
tPWH
TX_CLK/RX_CLK Pulse Width
High
468
ns
tPWL
TX_CLK/RX_CLK Pulse Width
Low
466
ns
Notes: 1) During AID interval, RX_CLK and TX_CLK stop for up to 140 us.
2) During Preamble state, RX_CLK stays at Low.
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