DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
35
Version: DM9801-DS-P02
March 20, 2000
SPI Serial Management Register Map (INTFSEL = 1, GPSI Mode)
Register
Address
Register Name
Access
Type
Default
Value
Description
1-0
CNTRL
RW
0x0005
Control Registers
3-2
STATUS
RW
0x0000
Status Registers
5-4
IMASK
RW
0x0000
Interrupt Mask Registers
7-6
ISTAT
RW
0x0000
Interrupt Status Registers
9-8
TX_PCOM_LO
RW
0x0000
Transmit PHY Communication Low Word
11-10
TX_PCOM_HI
RW
0x0000
Transmit PHY Communication High Word
13-12
RX_PCOM_LO
RW
0x0000
Receive PHY Communication Low Word
15-14
RX_PCOM_HI
RW
0x0000
Receive PHY Communication High Word
19-18
PEAK_NOISE
RW
0xFF04
PEAK Level and Noise Level Registers
17-16
NOISE_CNTRL_A
RW
0x8007
Noise Ceiling and Noise Floor Registers
21-20
NOISE_CNTRL_B
RW
0x00F4
Noise Events and Noise Attack Registers
22
FWENA
RW
0x00
Four Wire Enable and Link Disable Registers
24-23
Reserved
Reserved
25
AID_ADDRESS
RW
0x00
AID Address Register
27-26
AID_CNTRL
RW
0x4014
AID Interval and AID ISBI Registers
29-28
SYM_CNTRL
RW
0x1C2C
DATA ISBI Control Registers
31-30
TX_SIG_CNTRL
RW
0x4404
Transmit Pulse Control Registers
SPI Serial Management Control Register - Register 0 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
Description
0.7
AID_ADR_NEG
0,RW
AID Address Negotiation:
1= Stop AID address negotiation
0= Normal operation
0.6
CLR_NS_EVNT
0,RW
Clear Noise Event Register:
1= Clear the Noise Event Register
0= Normal operation
0.5
SLC_LVL_ADP
0,RW
Slice Level Adaptation:
1= Slice level adaptation is disabled (stopped).
0= Slice level adaptation is enabled
0.4
PWR_DWN
0,RW
Power Down:
Writing a 1 to this bit will cause DM9801 to enter Sleep mode
and power down all circuits except the oscillator and clock
generator circuit. To exit Sleep mode, write 0 to this bit position.
The prior configuration will be retained when the sleep state is
terminated, but the state machine will be reset
0.3
Reserved
0,RW
Reserved:
This bit must be written as 0
0.2
Speed
1,RW
Speed:
1= high speed
0= low speed
This bit indicates the network speed is set to high as selected
by the status of the SPDSEL pin during power-up/reset.
0.1
POWER
0,RW
Power:
1= high power
0= low power
This bit indicates the network power is set to high as selected
by the status of the PWRSEL pin during power-up/reset.
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