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DM9801 Datasheet(PDF) 40 Page - List of Unclassifed Manufacturers

Part # DM9801
Description  1M home Phonrline Network Physical Layer Single Chip Transceiver
PDF  61 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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DM9801 Datasheet(HTML) 40 Page - List of Unclassifed Manufacturers

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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
40
Preliminary
Version: DM9801-DS-P02
March 20, 2000
RX_PCOM Low A Register - Register 13 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
Description
13.7 –
13.0
RX_PCOM_LOA
0, RW
RX_PCOM_LOA:
The 15
th through the 8th bits of the 32-bit receive data field to be used
for out-of-band communications between PHY management entities.
A non-null receive PCOM will set the RX_PCOM_VAL bit in the ISTAT
register.
An access of the high byte of the RX_PCOM_HI register will clear the
RX_PCOM_VAL bit in the ISTAT register.
RX_PCOM High B Register - Register 14 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
Description
14.7 –
14.0
RX_PCOM_HIB
0, RW
RX_PCOM_HIB:
The 23
rd through the 16th bits of the 32-bit receive data field to be used
for out-of-band communications between PHY management entities.
A non-null receive PCOM will set the RX_PCOM_VAL bit in the ISTAT
register.
An access of the high byte of this register will clear the
RX_PCOM_VAL bit in the ISTAT register.
RX_PCOM High A Register - Register 15 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
Description
15.7 -
15.0
RX_PCOM_HIA
0, RW
RX_PCOM_HIA:
The MSB of the 32-bit receive data field to be used for out-of-band
communications between PHY management entities.
A non-null receive PCOM will set the RX_PCOM_VAL bit in the ISTAT
register.
An access of the high byte of this register will clear the
RX_PCOM_VAL bit in the ISTAT register.
Noise Level Register - Register 16 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
Description
16.7 -
16.0
NOISE_LEVEL
0x04, RW
NOISE LEVEL:
This is the digital value of the SLICE_LVL_NOISE output. It is
effectively a measure of the noise level on the wire. When auto-
adaptation is enabled (bit 5 of the Control register is false) this register
is updated with the current noise count every 50n Secs. When
adaptation is disabled, this register can be written and is used to
generate both the SLICE_LVL_NOISE and the SLICE_LVL_DATA
signals.
Peak Level Register - Register 17 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
Description
17.7 -
17.0
PEAK_LEVEL
0xFF, RW
Peak Level:
This is a measurement of the peak level of the last valid (non-collision)
AID received also, the maximum allowable value of the noise
measurement. If NOISE_LEVEL exceeds PEAK_LEVEL,
NOISE_LEVEL is reset to NOISE_FLOOR.



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